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OMAP: GPIO: clear/restore level/edge detect settings on mask/unmask

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If IRQ triggering is enabled, it can trigger a pending interrupt
even for masked interrupts.  Any pending GPIO interrupts can
prevent the powerdomain from hitting retention.

Problem found, reported and additional review and testing by Chunquiu
Wang.

Tested-by: Chunquiu Wang <cqwang@motorola.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Kevin Hilman 2009-06-04 15:57:10 -07:00
parent 6c5f80393b
commit 55b6019ae2
1 changed files with 6 additions and 0 deletions
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6
arch/arm/plat-omap/gpio.c
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@ -1189,6 +1189,7 @@ static void gpio_mask_irq(unsigned int irq)
struct gpio_bank *bank = get_irq_chip_data(irq);
_set_gpio_irqenable(bank, gpio, 0);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
}
static void gpio_unmask_irq(unsigned int irq)
@ -1196,6 +1197,11 @@ static void gpio_unmask_irq(unsigned int irq)
unsigned int gpio = irq - IH_GPIO_BASE;
struct gpio_bank *bank = get_irq_chip_data(irq);
unsigned int irq_mask = 1 << get_gpio_index(gpio);
struct irq_desc *desc = irq_to_desc(irq);
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
if (trigger)
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
/* For level-triggered GPIOs, the clearing must be done after
* the HW source is cleared, thus after the handler has run */