AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for irqpin module

Browse Source 
This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state.
By making it available to the driver, we make sure it gets enabled when
needed, and allow it to be managed by system or runtime PM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2015-01-06 20:56:05 +01:00 committed by Simon Horman
parent 8ac627fa8e
commit 56a215d66b
2 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -94,6 +94,7 @@ irqpin0: irqpin@e6900000 {
0 6 IRQ_TYPE_LEVEL_HIGH
0 7 IRQ_TYPE_LEVEL_HIGH
0 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@ -114,6 +115,7 @@ irqpin1: irqpin@e6900004 {
0 14 IRQ_TYPE_LEVEL_HIGH
0 15 IRQ_TYPE_LEVEL_HIGH
0 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@ -134,6 +136,7 @@ irqpin2: irqpin@e6900008 {
0 22 IRQ_TYPE_LEVEL_HIGH
0 23 IRQ_TYPE_LEVEL_HIGH
0 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@ -154,6 +157,7 @@ irqpin3: irqpin@e690000c {
0 30 IRQ_TYPE_LEVEL_HIGH
0 31 IRQ_TYPE_LEVEL_HIGH
0 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@ -698,5 +702,16 @@ SH73A0_CLK_KEYSC
clock-output-names =
"iic3", "iic4", "keysc";
};
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xe6150144 4>, <0xe615003c 4>;
clocks = <&cpg_clocks SH73A0_CLK_HP>;
#clock-cells = <1>;
clock-indices = <
SH73A0_CLK_INTCA0
>;
clock-output-names =
"intca0";
};
};
};

3
include/dt-bindings/clock/sh73a0-clock.h
View File

@ -76,4 +76,7 @@
#define SH73A0_CLK_IIC4 10
#define SH73A0_CLK_KEYSC 3
/* MSTP5 */
#define SH73A0_CLK_INTCA0 8
#endif