forked from luck/tmp_suning_uos_patched
Renesas ARM64 DT updates for v5.5 (take two)
- Video-Input and Serial-ATA support on RZ/G2N,
- Color Management Module support on various R-Car Gen3 SoCs,
- Initial support for the R-Car M3-W+ (r8a77961) SoC on the
Salvator-XS board.
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cNS0AQDofwzZRnNq8xUumbw9fg2I79qhVqqBFYpg+R8qV7qgQQD/WwOfSfE6UlCf
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=qA0S
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Merge tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM64 DT updates for v5.5 (take two)
- Video-Input and Serial-ATA support on RZ/G2N,
- Color Management Module support on various R-Car Gen3 SoCs,
- Initial support for the R-Car M3-W+ (r8a77961) SoC on the
Salvator-XS board.
* tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
arm64: dts: renesas: Add Renesas R8A77961 SoC support
arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960
dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
dt-bindings: power: Add r8a77961 SYSC power domain definitions
arm64: dts: renesas: r8a774b1: Add SATA controller node
arm64: dts: renesas: rcar-gen3: Add CMM units
arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support
Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
571d32c283
|
|
@ -12,6 +12,10 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
|
|||
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
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||||
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
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||||
dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-m3ulcb-kf.dtb
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||||
dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-salvator-xs.dtb
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||||
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb
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dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
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dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
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dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
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||||
|
|
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|||
|
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@ -1282,6 +1282,262 @@ msiof3: spi@e6c10000 {
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|||
status = "disabled";
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||||
};
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||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a774b1";
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||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 811>;
|
||||
renesas,id = <0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
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||||
|
||||
reg = <1>;
|
||||
|
||||
vin0csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin0>;
|
||||
};
|
||||
vin0csi40: endpoint@2 {
|
||||
reg = <2>;
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||||
remote-endpoint = <&csi40vin0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
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||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a774b1";
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||||
reg = <0 0xe6ef1000 0 0x1000>;
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||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 810>;
|
||||
renesas,id = <1>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin1csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin1>;
|
||||
};
|
||||
vin1csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&csi40vin1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a774b1";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 809>;
|
||||
renesas,id = <2>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin2csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin2>;
|
||||
};
|
||||
vin2csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&csi40vin2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a774b1";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 808>;
|
||||
renesas,id = <3>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin3csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin3>;
|
||||
};
|
||||
vin3csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&csi40vin3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a774b1";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 807>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 807>;
|
||||
renesas,id = <4>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin4csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin4>;
|
||||
};
|
||||
vin4csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&csi40vin4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin5: video@e6ef5000 {
|
||||
compatible = "renesas,vin-r8a774b1";
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 806>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 806>;
|
||||
renesas,id = <5>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin5csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin5>;
|
||||
};
|
||||
vin5csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&csi40vin5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin6: video@e6ef6000 {
|
||||
compatible = "renesas,vin-r8a774b1";
|
||||
reg = <0 0xe6ef6000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 805>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 805>;
|
||||
renesas,id = <6>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin6csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin6>;
|
||||
};
|
||||
vin6csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&csi40vin6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin7: video@e6ef7000 {
|
||||
compatible = "renesas,vin-r8a774b1";
|
||||
reg = <0 0xe6ef7000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 804>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 804>;
|
||||
renesas,id = <7>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin7csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi20vin7>;
|
||||
};
|
||||
vin7csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&csi40vin7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
/*
|
||||
* #sound-dai-cells is required
|
||||
|
|
@ -1900,6 +2156,17 @@ sdhi3: sd@ee160000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a774b1",
|
||||
"renesas,rcar-gen3-sata";
|
||||
reg = <0 0xee300000 0 0x200000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 815>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 815>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -2065,6 +2332,116 @@ fcpvi0: fcp@fe9af000 {
|
|||
resets = <&cpg 611>;
|
||||
};
|
||||
|
||||
csi20: csi2@fea80000 {
|
||||
compatible = "renesas,r8a774b1-csi2";
|
||||
reg = <0 0xfea80000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 714>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 714>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
csi20vin0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vin0csi20>;
|
||||
};
|
||||
csi20vin1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vin1csi20>;
|
||||
};
|
||||
csi20vin2: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&vin2csi20>;
|
||||
};
|
||||
csi20vin3: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&vin3csi20>;
|
||||
};
|
||||
csi20vin4: endpoint@4 {
|
||||
reg = <4>;
|
||||
remote-endpoint = <&vin4csi20>;
|
||||
};
|
||||
csi20vin5: endpoint@5 {
|
||||
reg = <5>;
|
||||
remote-endpoint = <&vin5csi20>;
|
||||
};
|
||||
csi20vin6: endpoint@6 {
|
||||
reg = <6>;
|
||||
remote-endpoint = <&vin6csi20>;
|
||||
};
|
||||
csi20vin7: endpoint@7 {
|
||||
reg = <7>;
|
||||
remote-endpoint = <&vin7csi20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
csi40: csi2@feaa0000 {
|
||||
compatible = "renesas,r8a774b1-csi2";
|
||||
reg = <0 0xfeaa0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 716>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 716>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
csi40vin0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vin0csi40>;
|
||||
};
|
||||
csi40vin1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vin1csi40>;
|
||||
};
|
||||
csi40vin2: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&vin2csi40>;
|
||||
};
|
||||
csi40vin3: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&vin3csi40>;
|
||||
};
|
||||
csi40vin4: endpoint@4 {
|
||||
reg = <4>;
|
||||
remote-endpoint = <&vin4csi40>;
|
||||
};
|
||||
csi40vin5: endpoint@5 {
|
||||
reg = <5>;
|
||||
remote-endpoint = <&vin5csi40>;
|
||||
};
|
||||
csi40vin6: endpoint@6 {
|
||||
reg = <6>;
|
||||
remote-endpoint = <&vin6csi40>;
|
||||
};
|
||||
csi40vin7: endpoint@7 {
|
||||
reg = <7>;
|
||||
remote-endpoint = <&vin7csi40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi0: hdmi@fead0000 {
|
||||
compatible = "renesas,r8a774b1-hdmi",
|
||||
"renesas,rcar-gen3-hdmi";
|
||||
|
|
|
|||
|
|
@ -2943,6 +2943,42 @@ fcpvd2: fcp@fea37000 {
|
|||
iommus = <&ipmmu_vi1 10>;
|
||||
};
|
||||
|
||||
cmm0: cmm@fea40000 {
|
||||
compatible = "renesas,r8a7795-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea40000 0 0x1000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 711>;
|
||||
resets = <&cpg 711>;
|
||||
};
|
||||
|
||||
cmm1: cmm@fea50000 {
|
||||
compatible = "renesas,r8a7795-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea50000 0 0x1000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 710>;
|
||||
resets = <&cpg 710>;
|
||||
};
|
||||
|
||||
cmm2: cmm@fea60000 {
|
||||
compatible = "renesas,r8a7795-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea60000 0 0x1000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 709>;
|
||||
resets = <&cpg 709>;
|
||||
};
|
||||
|
||||
cmm3: cmm@fea70000 {
|
||||
compatible = "renesas,r8a7795-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea70000 0 0x1000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 708>;
|
||||
resets = <&cpg 708>;
|
||||
};
|
||||
|
||||
csi20: csi2@fea80000 {
|
||||
compatible = "renesas,r8a7795-csi2";
|
||||
reg = <0 0xfea80000 0 0x10000>;
|
||||
|
|
@ -3146,7 +3182,10 @@ du: display@feb00000 {
|
|||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -2645,6 +2645,33 @@ vspi0: vsp@fe9a0000 {
|
|||
renesas,fcp = <&fcpvi0>;
|
||||
};
|
||||
|
||||
cmm0: cmm@fea40000 {
|
||||
compatible = "renesas,r8a7796-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea40000 0 0x1000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 711>;
|
||||
resets = <&cpg 711>;
|
||||
};
|
||||
|
||||
cmm1: cmm@fea50000 {
|
||||
compatible = "renesas,r8a7796-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea50000 0 0x1000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 710>;
|
||||
resets = <&cpg 710>;
|
||||
};
|
||||
|
||||
cmm2: cmm@fea60000 {
|
||||
compatible = "renesas,r8a7796-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea60000 0 0x1000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 709>;
|
||||
resets = <&cpg 709>;
|
||||
};
|
||||
|
||||
csi20: csi2@fea80000 {
|
||||
compatible = "renesas,r8a7796-csi2";
|
||||
reg = <0 0xfea80000 0 0x10000>;
|
||||
|
|
@ -2795,10 +2822,12 @@ du: display@feb00000 {
|
|||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>;
|
||||
clock-names = "du.0", "du.1", "du.2";
|
||||
status = "disabled";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
31
arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
Normal file
31
arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a77961.dtsi"
|
||||
#include "salvator-xs.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas Salvator-X 2nd version board based on r8a77961";
|
||||
compatible = "renesas,salvator-xs", "renesas,r8a77961";
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
memory@400000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x4 0x80000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x1 0x00000000>;
|
||||
};
|
||||
};
|
||||
723
arch/arm64/boot/dts/renesas/r8a77961.dtsi
Normal file
723
arch/arm64/boot/dts/renesas/r8a77961.dtsi
Normal file
|
|
@ -0,0 +1,723 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
|
||||
*
|
||||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a77961-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a77961-sysc.h>
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a77961";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
* Boards that provide audio clocks should override them.
|
||||
*/
|
||||
audio_clk_a: audio_clk_a {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
audio_clk_c: audio_clk_c {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
opp-microvolt = <900000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp-1700000000 {
|
||||
opp-hz = /bits/ 64 <1700000000>;
|
||||
opp-microvolt = <900000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <960000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1300000000 {
|
||||
opp-hz = /bits/ 64 <1300000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&a57_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a57_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&a53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&a53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&a53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
a57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77961_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
dynamic-power-coefficient = <854>;
|
||||
clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77961_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77961_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_1>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <277>;
|
||||
clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77961_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_1>;
|
||||
clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77961_PD_CA53_CPU2>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_1>;
|
||||
clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77961_PD_CA53_CPU3>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_1>;
|
||||
clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A77961_PD_CA57_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller-1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A77961_PD_CA53_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <400>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <4000>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_1: cpu-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <700>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <5000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External PCIe clock - can be overridden by the board */
|
||||
pcie_bus_clk: pcie_bus {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
|
||||
};
|
||||
|
||||
pmu_a57 {
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a57_0>, <&a57_1>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
rwdt: watchdog@e6020000 {
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
reg = <0 0xe6055400 0 0x50>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77961";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77961-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a77961-rst";
|
||||
reg = <0 0xe6160000 0 0x0200>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a77961-sysc";
|
||||
reg = <0 0xe6180000 0 0x0400>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c2: i2c@e6510000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0xe6510000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c4: i2c@e66d8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0xe66d8000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c_dvfs: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0xe60b0000 0 0x425>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
hscif1: serial@e6550000 {
|
||||
reg = <0 0xe6550000 0 0x60>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
reg = <0 0xe6590000 0 0x200>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
usb3_phy0: usb-phy@e65ee000 {
|
||||
reg = <0 0xe65ee000 0 0x90>;
|
||||
#phy-cells = <0>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pwm1: pwm@e6e31000 {
|
||||
reg = <0 0xe6e31000 0 8>;
|
||||
#pwm-cells = <2>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
scif1: serial@e6e68000 {
|
||||
reg = <0 0xe6e68000 0 64>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a77961",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>,
|
||||
<&cpg CPG_CORE R8A77961_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin5: video@e6ef5000 {
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin6: video@e6ef6000 {
|
||||
reg = <0 0xe6ef6000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin7: video@e6ef7000 {
|
||||
reg = <0 0xe6ef7000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
/* placeholder */
|
||||
rcar_sound,dvc {
|
||||
dvc0: dvc-0 { };
|
||||
dvc1: dvc-1 { };
|
||||
};
|
||||
|
||||
rcar_sound,src {
|
||||
src0: src-0 { };
|
||||
src1: src-1 { };
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi-0 { };
|
||||
ssi1: ssi-1 { };
|
||||
};
|
||||
};
|
||||
|
||||
xhci0: usb@ee000000 {
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
usb3_peri0: usb@ee020000 {
|
||||
reg = <0 0xee020000 0 0x400>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ohci1: usb@ee0a0000 {
|
||||
reg = <0 0xee0a0000 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ehci0: usb@ee080100 {
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ehci1: usb@ee0a0100 {
|
||||
reg = <0 0xee0a0100 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@ee080200 {
|
||||
reg = <0 0xee080200 0 0x700>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
usb2_phy1: usb-phy@ee0a0200 {
|
||||
reg = <0 0xee0a0200 0 0x700>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1010000 0 0x1000>,
|
||||
<0x0 0xf1020000 0 0x20000>,
|
||||
<0x0 0xf1040000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
pciec0: pcie@fe000000 {
|
||||
reg = <0 0xfe000000 0 0x80000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pciec1: pcie@ee800000 {
|
||||
reg = <0 0xee800000 0 0x80000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
csi20: csi2@fea80000 {
|
||||
reg = <0 0xfea80000 0 0x10000>;
|
||||
/* placeholder */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
csi40: csi2@feaa0000 {
|
||||
reg = <0 0xfeaa0000 0 0x10000>;
|
||||
/* placeholder */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi0: hdmi@fead0000 {
|
||||
reg = <0 0xfead0000 0 0x10000>;
|
||||
/* placeholder */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
port@2 {
|
||||
/* HDMI sound */
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
reg = <0 0xfeb00000 0 0x70000>;
|
||||
/* placeholder */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_hdmi0: endpoint {
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
/* External USB clocks - can be overridden by the board */
|
||||
usb3s0_clk: usb3s0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -2324,6 +2324,33 @@ fcpvi0: fcp@fe9af000 {
|
|||
resets = <&cpg 611>;
|
||||
};
|
||||
|
||||
cmm0: cmm@fea40000 {
|
||||
compatible = "renesas,r8a77965-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea40000 0 0x1000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 711>;
|
||||
resets = <&cpg 711>;
|
||||
};
|
||||
|
||||
cmm1: cmm@fea50000 {
|
||||
compatible = "renesas,r8a77965-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea50000 0 0x1000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 710>;
|
||||
resets = <&cpg 710>;
|
||||
};
|
||||
|
||||
cmm3: cmm@fea70000 {
|
||||
compatible = "renesas,r8a77965-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea70000 0 0x1000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 708>;
|
||||
resets = <&cpg 708>;
|
||||
};
|
||||
|
||||
csi20: csi2@fea80000 {
|
||||
compatible = "renesas,r8a77965-csi2";
|
||||
reg = <0 0xfea80000 0 0x10000>;
|
||||
|
|
@ -2471,10 +2498,12 @@ du: display@feb00000 {
|
|||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>;
|
||||
clock-names = "du.0", "du.1", "du.3";
|
||||
status = "disabled";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -1730,6 +1730,24 @@ fcpvd1: fcp@fea2f000 {
|
|||
iommus = <&ipmmu_vi0 9>;
|
||||
};
|
||||
|
||||
cmm0: cmm@fea40000 {
|
||||
compatible = "renesas,r8a77990-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea40000 0 0x1000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 711>;
|
||||
resets = <&cpg 711>;
|
||||
};
|
||||
|
||||
cmm1: cmm@fea50000 {
|
||||
compatible = "renesas,r8a77990-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea50000 0 0x1000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 710>;
|
||||
resets = <&cpg 710>;
|
||||
};
|
||||
|
||||
csi40: csi2@feaa0000 {
|
||||
compatible = "renesas,r8a77990-csi2";
|
||||
reg = <0 0xfeaa0000 0 0x10000>;
|
||||
|
|
@ -1771,7 +1789,10 @@ du: display@feb00000 {
|
|||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -994,6 +994,24 @@ fcpvd1: fcp@fea2f000 {
|
|||
iommus = <&ipmmu_vi0 9>;
|
||||
};
|
||||
|
||||
cmm0: cmm@fea40000 {
|
||||
compatible = "renesas,r8a77995-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea40000 0 0x1000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 711>;
|
||||
resets = <&cpg 711>;
|
||||
};
|
||||
|
||||
cmm1: cmm@fea50000 {
|
||||
compatible = "renesas,r8a77995-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0 0xfea50000 0 0x1000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 710>;
|
||||
resets = <&cpg 710>;
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a77995";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
|
|
@ -1004,7 +1022,10 @@ du: display@feb00000 {
|
|||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
65
include/dt-bindings/clock/r8a77961-cpg-mssr.h
Normal file
65
include/dt-bindings/clock/r8a77961-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77961 CPG Core Clocks */
|
||||
#define R8A77961_CLK_Z 0
|
||||
#define R8A77961_CLK_Z2 1
|
||||
#define R8A77961_CLK_ZR 2
|
||||
#define R8A77961_CLK_ZG 3
|
||||
#define R8A77961_CLK_ZTR 4
|
||||
#define R8A77961_CLK_ZTRD2 5
|
||||
#define R8A77961_CLK_ZT 6
|
||||
#define R8A77961_CLK_ZX 7
|
||||
#define R8A77961_CLK_S0D1 8
|
||||
#define R8A77961_CLK_S0D2 9
|
||||
#define R8A77961_CLK_S0D3 10
|
||||
#define R8A77961_CLK_S0D4 11
|
||||
#define R8A77961_CLK_S0D6 12
|
||||
#define R8A77961_CLK_S0D8 13
|
||||
#define R8A77961_CLK_S0D12 14
|
||||
#define R8A77961_CLK_S1D1 15
|
||||
#define R8A77961_CLK_S1D2 16
|
||||
#define R8A77961_CLK_S1D4 17
|
||||
#define R8A77961_CLK_S2D1 18
|
||||
#define R8A77961_CLK_S2D2 19
|
||||
#define R8A77961_CLK_S2D4 20
|
||||
#define R8A77961_CLK_S3D1 21
|
||||
#define R8A77961_CLK_S3D2 22
|
||||
#define R8A77961_CLK_S3D4 23
|
||||
#define R8A77961_CLK_LB 24
|
||||
#define R8A77961_CLK_CL 25
|
||||
#define R8A77961_CLK_ZB3 26
|
||||
#define R8A77961_CLK_ZB3D2 27
|
||||
#define R8A77961_CLK_ZB3D4 28
|
||||
#define R8A77961_CLK_CR 29
|
||||
#define R8A77961_CLK_CRD2 30
|
||||
#define R8A77961_CLK_SD0H 31
|
||||
#define R8A77961_CLK_SD0 32
|
||||
#define R8A77961_CLK_SD1H 33
|
||||
#define R8A77961_CLK_SD1 34
|
||||
#define R8A77961_CLK_SD2H 35
|
||||
#define R8A77961_CLK_SD2 36
|
||||
#define R8A77961_CLK_SD3H 37
|
||||
#define R8A77961_CLK_SD3 38
|
||||
#define R8A77961_CLK_SSP2 39
|
||||
#define R8A77961_CLK_SSP1 40
|
||||
#define R8A77961_CLK_SSPRS 41
|
||||
#define R8A77961_CLK_RPC 42
|
||||
#define R8A77961_CLK_RPCD2 43
|
||||
#define R8A77961_CLK_MSO 44
|
||||
#define R8A77961_CLK_CANFD 45
|
||||
#define R8A77961_CLK_HDMI 46
|
||||
#define R8A77961_CLK_CSI0 47
|
||||
/* CLK_CSIREF was removed */
|
||||
#define R8A77961_CLK_CP 49
|
||||
#define R8A77961_CLK_CPEX 50
|
||||
#define R8A77961_CLK_R 51
|
||||
#define R8A77961_CLK_OSC 52
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
|
||||
32
include/dt-bindings/power/r8a77961-sysc.h
Normal file
32
include/dt-bindings/power/r8a77961-sysc.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2019 Glider bvba
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77961_PD_CA57_CPU0 0
|
||||
#define R8A77961_PD_CA57_CPU1 1
|
||||
#define R8A77961_PD_CA53_CPU0 5
|
||||
#define R8A77961_PD_CA53_CPU1 6
|
||||
#define R8A77961_PD_CA53_CPU2 7
|
||||
#define R8A77961_PD_CA53_CPU3 8
|
||||
#define R8A77961_PD_CA57_SCU 12
|
||||
#define R8A77961_PD_CR7 13
|
||||
#define R8A77961_PD_A3VC 14
|
||||
#define R8A77961_PD_3DG_A 17
|
||||
#define R8A77961_PD_3DG_B 18
|
||||
#define R8A77961_PD_CA53_SCU 21
|
||||
#define R8A77961_PD_A3IR 24
|
||||
#define R8A77961_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77961_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
|
||||
Loading…
Reference in New Issue
Block a user