forked from luck/tmp_suning_uos_patched
sh: clockevent/clocksource/hrtimers/nohz TMU support.
This adds basic support for clockevents and clocksources, presently only implemented for TMU-based systems (which are the majority of SH-3 and SH-4 systems). The old NO_IDLE_HZ implementation is also dropped completely, the only users of this were on TMU-based systems anyways. More work needs to be done to generalize the TMU handling, in that the current implementation is rather tied to the notion of TMU0 and TMU1 utilization. Additionally, as more SH timers switch over to this scheme, we'll be able to gut most of the remaining system timer infrastructure that existed before. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
1ce7ddd5f4
commit
57be2b484a
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@ -52,6 +52,9 @@ config GENERIC_IOMAP
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config GENERIC_TIME
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def_bool n
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config GENERIC_CLOCKEVENTS
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def_bool n
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config SYS_SUPPORTS_APM_EMULATION
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bool
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@ -436,11 +439,11 @@ endmenu
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menu "Timer and clock configuration"
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if !GENERIC_TIME
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config SH_TMU
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bool "TMU timer support"
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depends on CPU_SH3 || CPU_SH4
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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default y
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help
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This enables the use of the TMU as the system timer.
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@ -459,8 +462,6 @@ config SH_MTU2
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help
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This enables the use of the MTU2 as the system timer.
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endif
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config SH_TIMER_IRQ
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int
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default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
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@ -468,24 +469,6 @@ config SH_TIMER_IRQ
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default "140" if CPU_SUBTYPE_SH7206
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default "16"
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config NO_IDLE_HZ
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bool "Dynamic tick timer"
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help
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Select this option if you want to disable continuous timer ticks
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and have them programmed to occur as required. This option saves
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power as the system can remain in idle state for longer.
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By default dynamic tick is disabled during the boot, and can be
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manually enabled with:
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echo 1 > /sys/devices/system/timer/timer0/dyn_tick
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Alternatively, if you want dynamic tick automatically enabled
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during boot, pass "dyntick=enable" via the kernel command string.
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Please note that dynamic tick may affect the accuracy of
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timekeeping on some platforms depending on the implementation.
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config SH_PCLK_FREQ
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int "Peripheral clock frequency (in Hz)"
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default "27000000" if CPU_SUBTYPE_SH73180 || CPU_SUBTYPE_SH7343
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@ -509,6 +492,8 @@ config SH_CLK_MD
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help
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MD2 - MD0 pin setting.
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source "kernel/time/Kconfig"
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endmenu
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menu "CPU Frequency scaling"
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@ -16,6 +16,7 @@
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#include <linux/kallsyms.h>
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#include <linux/kexec.h>
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#include <linux/kdebug.h>
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#include <linux/tick.h>
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#include <asm/uaccess.h>
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#include <asm/mmu_context.h>
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#include <asm/pgalloc.h>
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@ -60,8 +61,10 @@ void cpu_idle(void)
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if (!idle)
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idle = default_idle;
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tick_nohz_stop_sched_tick();
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while (!need_resched())
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idle();
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tick_nohz_restart_sched_tick();
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preempt_enable_no_resched();
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schedule();
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
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* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
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* Copyright (C) 2002 - 2006 Paul Mundt
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* Copyright (C) 2002 - 2007 Paul Mundt
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* Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
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*
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* Some code taken from i386 version.
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@ -15,6 +15,7 @@
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#include <linux/profile.h>
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#include <linux/timex.h>
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#include <linux/sched.h>
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#include <linux/clockchips.h>
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#include <asm/clock.h>
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#include <asm/rtc.h>
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#include <asm/timer.h>
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@ -38,6 +39,14 @@ static int null_rtc_set_time(const time_t secs)
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return 0;
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}
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/*
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* Null high precision timer functions for systems lacking one.
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*/
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static cycle_t null_hpt_read(void)
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{
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return 0;
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}
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void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
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int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
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@ -101,6 +110,7 @@ int do_settimeofday(struct timespec *tv)
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EXPORT_SYMBOL(do_settimeofday);
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#endif /* !CONFIG_GENERIC_TIME */
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#ifndef CONFIG_GENERIC_CLOCKEVENTS
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/* last time the RTC clock got updated */
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static long last_rtc_update;
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@ -138,6 +148,7 @@ void handle_timer_tick(void)
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last_rtc_update = xtime.tv_sec - 600;
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}
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}
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#endif /* !CONFIG_GENERIC_CLOCKEVENTS */
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#ifdef CONFIG_PM
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int timer_suspend(struct sys_device *dev, pm_message_t state)
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@ -168,108 +179,6 @@ static struct sysdev_class timer_sysclass = {
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.resume = timer_resume,
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};
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#ifdef CONFIG_NO_IDLE_HZ
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static int timer_dyn_tick_enable(void)
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{
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struct dyn_tick_timer *dyn_tick = sys_timer->dyn_tick;
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unsigned long flags;
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int ret = -ENODEV;
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if (dyn_tick) {
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spin_lock_irqsave(&dyn_tick->lock, flags);
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ret = 0;
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if (!(dyn_tick->state & DYN_TICK_ENABLED)) {
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ret = dyn_tick->enable();
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if (ret == 0)
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dyn_tick->state |= DYN_TICK_ENABLED;
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}
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spin_unlock_irqrestore(&dyn_tick->lock, flags);
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}
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return ret;
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}
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static int timer_dyn_tick_disable(void)
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{
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struct dyn_tick_timer *dyn_tick = sys_timer->dyn_tick;
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unsigned long flags;
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int ret = -ENODEV;
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if (dyn_tick) {
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spin_lock_irqsave(&dyn_tick->lock, flags);
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ret = 0;
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if (dyn_tick->state & DYN_TICK_ENABLED) {
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ret = dyn_tick->disable();
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if (ret == 0)
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dyn_tick->state &= ~DYN_TICK_ENABLED;
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}
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spin_unlock_irqrestore(&dyn_tick->lock, flags);
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}
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return ret;
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}
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/*
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* Reprogram the system timer for at least the calculated time interval.
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* This function should be called from the idle thread with IRQs disabled,
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* immediately before sleeping.
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*/
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void timer_dyn_reprogram(void)
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{
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struct dyn_tick_timer *dyn_tick = sys_timer->dyn_tick;
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unsigned long next, seq, flags;
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if (!dyn_tick)
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return;
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spin_lock_irqsave(&dyn_tick->lock, flags);
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if (dyn_tick->state & DYN_TICK_ENABLED) {
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next = next_timer_interrupt();
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do {
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seq = read_seqbegin(&xtime_lock);
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dyn_tick->reprogram(next - jiffies);
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} while (read_seqretry(&xtime_lock, seq));
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}
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spin_unlock_irqrestore(&dyn_tick->lock, flags);
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}
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static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf)
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{
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return sprintf(buf, "%i\n",
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(sys_timer->dyn_tick->state & DYN_TICK_ENABLED) >> 1);
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}
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static ssize_t timer_set_dyn_tick(struct sys_device *dev, const char *buf,
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size_t count)
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{
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unsigned int enable = simple_strtoul(buf, NULL, 2);
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if (enable)
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timer_dyn_tick_enable();
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else
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timer_dyn_tick_disable();
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return count;
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}
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static SYSDEV_ATTR(dyn_tick, 0644, timer_show_dyn_tick, timer_set_dyn_tick);
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/*
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* dyntick=enable|disable
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*/
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static char dyntick_str[4] __initdata = "";
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static int __init dyntick_setup(char *str)
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{
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if (str)
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strlcpy(dyntick_str, str, sizeof(dyntick_str));
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return 1;
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}
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__setup("dyntick=", dyntick_setup);
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#endif
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static int __init timer_init_sysfs(void)
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{
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int ret = sysdev_class_register(&timer_sysclass);
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return ret;
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sys_timer->dev.cls = &timer_sysclass;
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ret = sysdev_register(&sys_timer->dev);
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#ifdef CONFIG_NO_IDLE_HZ
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if (ret == 0 && sys_timer->dyn_tick) {
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ret = sysdev_create_file(&sys_timer->dev, &attr_dyn_tick);
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/*
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* Turn on dynamic tick after calibrate delay
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* for correct bogomips
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*/
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if (ret == 0 && dyntick_str[0] == 'e')
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ret = timer_dyn_tick_enable();
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}
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#endif
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return ret;
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return sysdev_register(&sys_timer->dev);
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}
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device_initcall(timer_init_sysfs);
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void (*board_time_init)(void);
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/*
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* Shamelessly based on the MIPS and Sparc64 work.
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*/
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static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
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unsigned long sh_hpt_frequency = 0;
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#define NSEC_PER_CYC_SHIFT 10
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struct clocksource clocksource_sh = {
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.name = "SuperH",
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.rating = 200,
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.mask = CLOCKSOURCE_MASK(32),
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.read = null_hpt_read,
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.shift = 16,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init init_sh_clocksource(void)
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{
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if (!sh_hpt_frequency || clocksource_sh.read == null_hpt_read)
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return;
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clocksource_sh.mult = clocksource_hz2mult(sh_hpt_frequency,
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clocksource_sh.shift);
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timer_ticks_per_nsec_quotient =
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clocksource_hz2mult(sh_hpt_frequency, NSEC_PER_CYC_SHIFT);
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clocksource_register(&clocksource_sh);
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}
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#ifdef CONFIG_GENERIC_TIME
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unsigned long long sched_clock(void)
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{
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unsigned long long ticks = clocksource_sh.read();
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return (ticks * timer_ticks_per_nsec_quotient) >> NSEC_PER_CYC_SHIFT;
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}
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#endif
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void __init time_init(void)
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{
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if (board_time_init)
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sys_timer = get_sys_timer();
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printk(KERN_INFO "Using %s for system timer\n", sys_timer->name);
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#ifdef CONFIG_NO_IDLE_HZ
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if (sys_timer->dyn_tick)
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spin_lock_init(&sys_timer->dyn_tick->lock);
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#endif
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if (sys_timer->ops->read)
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clocksource_sh.read = sys_timer->ops->read;
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init_sh_clocksource();
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if (sh_hpt_frequency)
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printk("Using %lu.%03lu MHz high precision timer.\n",
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((sh_hpt_frequency + 500) / 1000) / 1000,
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((sh_hpt_frequency + 500) / 1000) % 1000);
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#if defined(CONFIG_SH_KGDB)
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/*
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@ -1,7 +1,7 @@
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/*
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* arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
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*
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* Copyright (C) 2005 Paul Mundt
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* Copyright (C) 2005 - 2007 Paul Mundt
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*
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* TMU handling code hacked out of arch/sh/kernel/time.c
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*
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@ -18,6 +18,7 @@
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/seqlock.h>
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#include <linux/clockchips.h>
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#include <asm/timer.h>
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#include <asm/rtc.h>
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#include <asm/io.h>
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@ -25,56 +26,75 @@
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#include <asm/clock.h>
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#define TMU_TOCR_INIT 0x00
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#define TMU0_TCR_INIT 0x0020
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#define TMU_TSTR_INIT 1
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#define TMU_TCR_INIT 0x0020
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#define TMU0_TCR_CALIB 0x0000
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static unsigned long tmu_timer_get_offset(void)
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static int tmu_timer_start(void)
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{
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int count;
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static int count_p = 0x7fffffff; /* for the first call after boot */
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static unsigned long jiffies_p = 0;
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/*
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* cache volatile jiffies temporarily; we have IRQs turned off.
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*/
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unsigned long jiffies_t;
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/* timer count may underflow right here */
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count = ctrl_inl(TMU0_TCNT); /* read the latched count */
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jiffies_t = jiffies;
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/*
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* avoiding timer inconsistencies (they are rare, but they happen)...
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* there is one kind of problem that must be avoided here:
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* 1. the timer counter underflows
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*/
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if (jiffies_t == jiffies_p) {
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if (count > count_p) {
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/* the nutcase */
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if (ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
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count -= LATCH;
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} else {
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printk("%s (): hardware timer problem?\n",
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__FUNCTION__);
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}
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}
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} else
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jiffies_p = jiffies_t;
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count_p = count;
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count = ((LATCH-1) - count) * TICK_SIZE;
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count = (count + LATCH/2) / LATCH;
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return count;
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ctrl_outb(ctrl_inb(TMU_TSTR) | 0x3, TMU_TSTR);
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return 0;
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}
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static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload)
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{
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ctrl_outl(interval, TMU0_TCNT);
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/*
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* TCNT reloads from TCOR on underflow, clear it if we don't
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* intend to auto-reload
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*/
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if (reload)
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ctrl_outl(interval, TMU0_TCOR);
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else
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ctrl_outl(0, TMU0_TCOR);
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tmu_timer_start();
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}
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static int tmu_timer_stop(void)
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{
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ctrl_outb(ctrl_inb(TMU_TSTR) & ~0x3, TMU_TSTR);
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return 0;
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}
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static cycle_t tmu_timer_read(void)
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{
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return ~ctrl_inl(TMU1_TCNT);
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}
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static int tmu_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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tmu0_timer_set_interval(cycles, 1);
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return 0;
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}
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static void tmu_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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ctrl_outl(ctrl_inl(TMU0_TCNT), TMU0_TCOR);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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ctrl_outl(0, TMU0_TCOR);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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break;
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}
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}
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static struct clock_event_device tmu0_clockevent = {
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.name = "tmu0",
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = tmu_set_mode,
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.set_next_event = tmu_set_next_event,
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};
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static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
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{
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struct clock_event_device *evt = &tmu0_clockevent;
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unsigned long timer_status;
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/* Clear UNF bit */
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@ -82,72 +102,76 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
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timer_status &= ~0x100;
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ctrl_outw(timer_status, TMU0_TCR);
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/*
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* Here we are in the timer irq handler. We just have irqs locally
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* disabled but we don't know if the timer_bh is running on the other
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* CPU. We need to avoid to SMP race with it. NOTE: we don' t need
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* the irq version of write_lock because as just said we have irq
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* locally disabled. -arca
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*/
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write_seqlock(&xtime_lock);
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||||
handle_timer_tick();
|
||||
write_sequnlock(&xtime_lock);
|
||||
evt->event_handler(evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction tmu_irq = {
|
||||
.name = "timer",
|
||||
static struct irqaction tmu0_irq = {
|
||||
.name = "periodic timer",
|
||||
.handler = tmu_timer_interrupt,
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.mask = CPU_MASK_NONE,
|
||||
};
|
||||
|
||||
static void tmu_clk_init(struct clk *clk)
|
||||
static void tmu0_clk_init(struct clk *clk)
|
||||
{
|
||||
u8 divisor = TMU0_TCR_INIT & 0x7;
|
||||
ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
|
||||
u8 divisor = TMU_TCR_INIT & 0x7;
|
||||
ctrl_outw(TMU_TCR_INIT, TMU0_TCR);
|
||||
clk->rate = clk->parent->rate / (4 << (divisor << 1));
|
||||
}
|
||||
|
||||
static void tmu_clk_recalc(struct clk *clk)
|
||||
static void tmu0_clk_recalc(struct clk *clk)
|
||||
{
|
||||
u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
|
||||
clk->rate = clk->parent->rate / (4 << (divisor << 1));
|
||||
}
|
||||
|
||||
static struct clk_ops tmu_clk_ops = {
|
||||
.init = tmu_clk_init,
|
||||
.recalc = tmu_clk_recalc,
|
||||
static struct clk_ops tmu0_clk_ops = {
|
||||
.init = tmu0_clk_init,
|
||||
.recalc = tmu0_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk tmu0_clk = {
|
||||
.name = "tmu0_clk",
|
||||
.ops = &tmu_clk_ops,
|
||||
.ops = &tmu0_clk_ops,
|
||||
};
|
||||
|
||||
static int tmu_timer_start(void)
|
||||
static void tmu1_clk_init(struct clk *clk)
|
||||
{
|
||||
ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
|
||||
return 0;
|
||||
u8 divisor = TMU_TCR_INIT & 0x7;
|
||||
ctrl_outw(divisor, TMU1_TCR);
|
||||
clk->rate = clk->parent->rate / (4 << (divisor << 1));
|
||||
}
|
||||
|
||||
static int tmu_timer_stop(void)
|
||||
static void tmu1_clk_recalc(struct clk *clk)
|
||||
{
|
||||
ctrl_outb(0, TMU_TSTR);
|
||||
return 0;
|
||||
u8 divisor = ctrl_inw(TMU1_TCR) & 0x7;
|
||||
clk->rate = clk->parent->rate / (4 << (divisor << 1));
|
||||
}
|
||||
|
||||
static struct clk_ops tmu1_clk_ops = {
|
||||
.init = tmu1_clk_init,
|
||||
.recalc = tmu1_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk tmu1_clk = {
|
||||
.name = "tmu1_clk",
|
||||
.ops = &tmu1_clk_ops,
|
||||
};
|
||||
|
||||
static int tmu_timer_init(void)
|
||||
{
|
||||
unsigned long interval;
|
||||
unsigned long frequency;
|
||||
|
||||
setup_irq(CONFIG_SH_TIMER_IRQ, &tmu_irq);
|
||||
setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
|
||||
|
||||
tmu0_clk.parent = clk_get(NULL, "module_clk");
|
||||
tmu1_clk.parent = clk_get(NULL, "module_clk");
|
||||
|
||||
/* Start TMU0 */
|
||||
tmu_timer_stop();
|
||||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
|
@ -155,15 +179,29 @@ static int tmu_timer_init(void)
|
|||
#endif
|
||||
|
||||
clk_register(&tmu0_clk);
|
||||
clk_register(&tmu1_clk);
|
||||
clk_enable(&tmu0_clk);
|
||||
clk_enable(&tmu1_clk);
|
||||
|
||||
interval = (clk_get_rate(&tmu0_clk) + HZ / 2) / HZ;
|
||||
printk(KERN_INFO "Interval = %ld\n", interval);
|
||||
frequency = clk_get_rate(&tmu0_clk);
|
||||
interval = (frequency + HZ / 2) / HZ;
|
||||
|
||||
ctrl_outl(interval, TMU0_TCOR);
|
||||
ctrl_outl(interval, TMU0_TCNT);
|
||||
sh_hpt_frequency = clk_get_rate(&tmu1_clk);
|
||||
ctrl_outl(~0, TMU1_TCNT);
|
||||
ctrl_outl(~0, TMU1_TCOR);
|
||||
|
||||
tmu_timer_start();
|
||||
tmu0_timer_set_interval(interval, 1);
|
||||
|
||||
tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
|
||||
tmu0_clockevent.shift);
|
||||
tmu0_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(-1, &tmu0_clockevent);
|
||||
tmu0_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(1, &tmu0_clockevent);
|
||||
|
||||
tmu0_clockevent.cpumask = cpumask_of_cpu(0);
|
||||
|
||||
clockevents_register_device(&tmu0_clockevent);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -172,9 +210,7 @@ struct sys_timer_ops tmu_timer_ops = {
|
|||
.init = tmu_timer_init,
|
||||
.start = tmu_timer_start,
|
||||
.stop = tmu_timer_stop,
|
||||
#ifndef CONFIG_GENERIC_TIME
|
||||
.get_offset = tmu_timer_get_offset,
|
||||
#endif
|
||||
.read = tmu_timer_read,
|
||||
};
|
||||
|
||||
struct sys_timer tmu_timer = {
|
||||
|
|
|
@ -2,12 +2,14 @@
|
|||
#define __ASM_SH_TIMER_H
|
||||
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <asm/cpu/timer.h>
|
||||
|
||||
struct sys_timer_ops {
|
||||
int (*init)(void);
|
||||
int (*start)(void);
|
||||
int (*stop)(void);
|
||||
cycle_t (*read)(void);
|
||||
#ifndef CONFIG_GENERIC_TIME
|
||||
unsigned long (*get_offset)(void);
|
||||
#endif
|
||||
|
@ -18,29 +20,8 @@ struct sys_timer {
|
|||
|
||||
struct sys_device dev;
|
||||
struct sys_timer_ops *ops;
|
||||
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
struct dyn_tick_timer *dyn_tick;
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
#define DYN_TICK_ENABLED (1 << 1)
|
||||
|
||||
struct dyn_tick_timer {
|
||||
spinlock_t lock;
|
||||
unsigned int state; /* Current state */
|
||||
int (*enable)(void); /* Enables dynamic tick */
|
||||
int (*disable)(void); /* Disables dynamic tick */
|
||||
void (*reprogram)(unsigned long); /* Reprograms the timer */
|
||||
int (*handler)(int, void *);
|
||||
};
|
||||
|
||||
void timer_dyn_reprogram(void);
|
||||
#else
|
||||
#define timer_dyn_reprogram() do { } while (0)
|
||||
#endif
|
||||
|
||||
#define TICK_SIZE (tick_nsec / 1000)
|
||||
|
||||
extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
|
||||
|
@ -58,5 +39,7 @@ struct sys_timer *get_sys_timer(void);
|
|||
|
||||
/* arch/sh/kernel/time.c */
|
||||
void handle_timer_tick(void);
|
||||
extern unsigned long sh_hpt_frequency;
|
||||
extern struct clocksource clocksource_sh;
|
||||
|
||||
#endif /* __ASM_SH_TIMER_H */
|
||||
|
|
Loading…
Reference in New Issue
Block a user