forked from luck/tmp_suning_uos_patched
sh: multiple vectors per irq - sh7785
Update intc tables and platform data to use one linux irq per maskable interrupt source instead of keeping the one-to-one mapping between vectors and linux irqs. This fixes potential irq masking issues for sh7785 hardware blocks such as SCIF/DMAC/PCIC5/MMCIF/GDTA/FLCTL/GPIO Signed-off-by: Magnus Damm <damm@igel.co.jp> Tested-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
a842fb2d11
commit
57e41c86e2
@ -20,18 +20,13 @@ static struct plat_sci_port sci_platform_data[] = {
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.mapbase = 0xffea0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 40, 41, 43, 42 },
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.irqs = { 40, 40, 40, 40 },
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}, {
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.mapbase = 0xffeb0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 44, 45, 47, 46 },
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},
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/*
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* The rest of these all have multiplexed IRQs
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*/
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{
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.irqs = { 44, 44, 44, 44 },
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}, {
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.mapbase = 0xffec0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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@ -91,33 +86,19 @@ enum {
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IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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WDT,
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TMU0, TMU1, TMU2, TMU2_TICPI,
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HUDI,
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DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
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DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
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DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
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HSPI,
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WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
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HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
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SCIF2, SCIF3, SCIF4, SCIF5,
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PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
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PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
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SIOF,
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MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
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DU,
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GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
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PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
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SIOF, MMCIF, DU, GDTA,
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TMU3, TMU4, TMU5,
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SSI0, SSI1,
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HAC0, HAC1,
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FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
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GPIOI0, GPIOI1, GPIOI2, GPIOI3,
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FLCTL, GPIO,
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/* interrupt groups */
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TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
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PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
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TMU012, TMU345
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};
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static struct intc_vect vectors[] __initdata = {
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@ -125,57 +106,45 @@ static struct intc_vect vectors[] __initdata = {
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INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
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INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
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INTC_VECT(HUDI, 0x600),
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INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
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INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
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INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
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INTC_VECT(DMAC0_DMAE, 0x6e0),
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INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
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INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
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INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
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INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
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INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
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INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
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INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
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INTC_VECT(DMAC1_DMAE, 0x940),
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INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
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INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
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INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
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INTC_VECT(DMAC0, 0x6e0),
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INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
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INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
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INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
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INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
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INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
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INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
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INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
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INTC_VECT(DMAC1, 0x940),
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INTC_VECT(HSPI, 0x960),
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INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
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INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
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INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
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INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
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INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
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INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
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INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
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INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
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INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
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INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
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INTC_VECT(SIOF, 0xc00),
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INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
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INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
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INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
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INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
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INTC_VECT(DU, 0xd80),
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INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
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INTC_VECT(GDTA_GAERI, 0xde0),
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INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
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INTC_VECT(GDTA, 0xde0),
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INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
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INTC_VECT(TMU5, 0xe40),
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INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
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INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
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INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
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INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
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INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
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INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
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INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
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INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
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INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
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INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
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INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
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DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
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DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
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INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
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INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
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INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
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INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
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INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
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FLCTL_FLTRQ0, FLCTL_FLTRQ1),
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INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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