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MIPS: RM7000: Make use of cache_op() instead of inline asm

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Small cleanup of the cache code to get rid of inline asm, in preparation
to give tertiary cache support.

Signed-off-by: Ricardo Mendoza <ricmm@gentoo.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1476/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ricardo Mendoza 2010-07-19 04:59:59 +01:00 committed by Ralf Baechle
parent 65ab2826c4
commit 58a6d45193
1 changed files with 2 additions and 10 deletions
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12
arch/mips/mm/sc-rm7k.c
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@ -95,16 +95,8 @@ static __cpuinit void __rm7k_sc_enable(void)
write_c0_taglo(0);
write_c0_taghi(0);
for (i = 0; i < scache_size; i += sc_lsize) {
__asm__ __volatile__ (
".set noreorder\n\t"
".set mips3\n\t"
"cache %1, (%0)\n\t"
".set mips0\n\t"
".set reorder"
:
: "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
}
for (i = 0; i < scache_size; i += sc_lsize)
cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
}
static __cpuinit void rm7k_sc_enable(void)