forked from luck/tmp_suning_uos_patched
arm: plat-orion: use mv_mbus_dram_info() in PCIe code
The PCIe code was directly accessing the orion_mbus_dram_info structure to get access to a description of the SDRAM chip selects in order to configure the PCIe -> SDRAM address decoding windows. However, with the introduction of the orion-mbus driver, we are going to remove this global structure and instead leave only the exported mv_mbus_dram_info() function to access this description of the SDRAM chip selects. Therefore, we simply switch to using this API. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base)
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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* WIN[0-3] -> DRAM bank[0-3]
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*/
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static void __init orion_pcie_setup_wins(void __iomem *base,
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struct mbus_dram_target_info *dram)
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static void __init orion_pcie_setup_wins(void __iomem *base)
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{
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const struct mbus_dram_target_info *dram;
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u32 size;
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int i;
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dram = mv_mbus_dram_info();
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/*
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* First, disable and clear BARs and windows.
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*/
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@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
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*/
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size = 0;
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for (i = 0; i < dram->num_cs; i++) {
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struct mbus_dram_window *cs = dram->cs + i;
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const struct mbus_dram_window *cs = dram->cs + i;
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writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
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writel(0, base + PCIE_WIN04_REMAP_OFF(i));
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@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base)
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/*
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* Point PCIe unit MBUS decode windows to DRAM space.
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*/
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orion_pcie_setup_wins(base, &orion_mbus_dram_info);
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orion_pcie_setup_wins(base);
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/*
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* Master + slave enable.
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