forked from luck/tmp_suning_uos_patched
[ARM] tegra: Add IRQ support
v2: fixes from Russell King - include linux/io.h instead of asm/io.h and mach/io.h Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
This commit is contained in:
Erik Gilling
parent
c5f800656b
commit
5ad36c5f0e
@ -1,2 +1,3 @@
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obj-y += common.o
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obj-y += io.o
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obj-y += irq.o
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173
arch/arm/mach-tegra/include/mach/irqs.h
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173
arch/arm/mach-tegra/include/mach/irqs.h
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/*
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* arch/arm/mach-tegra/include/mach/irqs.h
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Erik Gilling <konkers@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_IRQS_H
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#define __MACH_TEGRA_IRQS_H
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#define INT_GIC_BASE 0
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#define IRQ_LOCALTIMER 29
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/* Primary Interrupt Controller */
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#define INT_PRI_BASE (INT_GIC_BASE + 32)
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#define INT_TMR1 (INT_PRI_BASE + 0)
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#define INT_TMR2 (INT_PRI_BASE + 1)
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#define INT_RTC (INT_PRI_BASE + 2)
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#define INT_I2S2 (INT_PRI_BASE + 3)
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#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4)
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#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5)
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#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6)
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#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7)
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#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8)
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#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9)
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#define INT_VDE_BSE_V (INT_PRI_BASE + 10)
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#define INT_VDE_BSE_A (INT_PRI_BASE + 11)
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#define INT_VDE_SXE (INT_PRI_BASE + 12)
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#define INT_I2S1 (INT_PRI_BASE + 13)
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#define INT_SDMMC1 (INT_PRI_BASE + 14)
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#define INT_SDMMC2 (INT_PRI_BASE + 15)
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#define INT_XIO (INT_PRI_BASE + 16)
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#define INT_VDE (INT_PRI_BASE + 17)
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#define INT_AVP_UCQ (INT_PRI_BASE + 18)
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#define INT_SDMMC3 (INT_PRI_BASE + 19)
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#define INT_USB (INT_PRI_BASE + 20)
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#define INT_USB2 (INT_PRI_BASE + 21)
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#define INT_PRI_RES_22 (INT_PRI_BASE + 22)
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#define INT_EIDE (INT_PRI_BASE + 23)
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#define INT_NANDFLASH (INT_PRI_BASE + 24)
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#define INT_VCP (INT_PRI_BASE + 25)
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#define INT_APB_DMA (INT_PRI_BASE + 26)
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#define INT_AHB_DMA (INT_PRI_BASE + 27)
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#define INT_GNT_0 (INT_PRI_BASE + 28)
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#define INT_GNT_1 (INT_PRI_BASE + 29)
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#define INT_OWR (INT_PRI_BASE + 30)
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#define INT_SDMMC4 (INT_PRI_BASE + 31)
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/* Secondary Interrupt Controller */
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#define INT_SEC_BASE (INT_PRI_BASE + 32)
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#define INT_GPIO1 (INT_SEC_BASE + 0)
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#define INT_GPIO2 (INT_SEC_BASE + 1)
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#define INT_GPIO3 (INT_SEC_BASE + 2)
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#define INT_GPIO4 (INT_SEC_BASE + 3)
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#define INT_UARTA (INT_SEC_BASE + 4)
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#define INT_UARTB (INT_SEC_BASE + 5)
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#define INT_I2C (INT_SEC_BASE + 6)
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#define INT_SPI (INT_SEC_BASE + 7)
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#define INT_TWC (INT_SEC_BASE + 8)
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#define INT_TMR3 (INT_SEC_BASE + 9)
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#define INT_TMR4 (INT_SEC_BASE + 10)
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#define INT_FLOW_RSM0 (INT_SEC_BASE + 11)
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#define INT_FLOW_RSM1 (INT_SEC_BASE + 12)
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#define INT_SPDIF (INT_SEC_BASE + 13)
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#define INT_UARTC (INT_SEC_BASE + 14)
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#define INT_MIPI (INT_SEC_BASE + 15)
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#define INT_EVENTA (INT_SEC_BASE + 16)
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#define INT_EVENTB (INT_SEC_BASE + 17)
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#define INT_EVENTC (INT_SEC_BASE + 18)
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#define INT_EVENTD (INT_SEC_BASE + 19)
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#define INT_VFIR (INT_SEC_BASE + 20)
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#define INT_DVC (INT_SEC_BASE + 21)
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#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
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#define INT_GPIO5 (INT_SEC_BASE + 23)
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#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24)
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#define INT_CPU2_PMU_INTR (INT_SEC_BASE + 25)
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#define INT_SEC_RES_26 (INT_SEC_BASE + 26)
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#define INT_S_LINK1 (INT_SEC_BASE + 27)
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#define INT_APB_DMA_COP (INT_SEC_BASE + 28)
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#define INT_AHB_DMA_COP (INT_SEC_BASE + 29)
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#define INT_DMA_TX (INT_SEC_BASE + 30)
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#define INT_DMA_RX (INT_SEC_BASE + 31)
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/* Tertiary Interrupt Controller */
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#define INT_TRI_BASE (INT_SEC_BASE + 32)
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#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0)
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#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1)
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#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2)
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#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3)
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#define INT_MPE_GENERAL (INT_TRI_BASE + 4)
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#define INT_VI_GENERAL (INT_TRI_BASE + 5)
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#define INT_EPP_GENERAL (INT_TRI_BASE + 6)
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#define INT_ISP_GENERAL (INT_TRI_BASE + 7)
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#define INT_2D_GENERAL (INT_TRI_BASE + 8)
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#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9)
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#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10)
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#define INT_HDMI (INT_TRI_BASE + 11)
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#define INT_TVO_GENERAL (INT_TRI_BASE + 12)
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#define INT_MC_GENERAL (INT_TRI_BASE + 13)
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#define INT_EMC_GENERAL (INT_TRI_BASE + 14)
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#define INT_TRI_RES_15 (INT_TRI_BASE + 15)
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#define INT_TRI_RES_16 (INT_TRI_BASE + 16)
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#define INT_AC97 (INT_TRI_BASE + 17)
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#define INT_SPI_2 (INT_TRI_BASE + 18)
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#define INT_SPI_3 (INT_TRI_BASE + 19)
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#define INT_I2C2 (INT_TRI_BASE + 20)
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#define INT_KBC (INT_TRI_BASE + 21)
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#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
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#define INT_GPIO6 (INT_TRI_BASE + 23)
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#define INT_TVDAC (INT_TRI_BASE + 24)
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#define INT_GPIO7 (INT_TRI_BASE + 25)
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#define INT_UARTD (INT_TRI_BASE + 26)
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#define INT_UARTE (INT_TRI_BASE + 27)
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#define INT_I2C3 (INT_TRI_BASE + 28)
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#define INT_SPI_4 (INT_TRI_BASE + 29)
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#define INT_TRI_RES_30 (INT_TRI_BASE + 30)
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#define INT_SW_RESERVED (INT_TRI_BASE + 31)
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/* Quaternary Interrupt Controller */
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#define INT_QUAD_BASE (INT_TRI_BASE + 32)
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#define INT_SNOR (INT_QUAD_BASE + 0)
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#define INT_USB3 (INT_QUAD_BASE + 1)
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#define INT_PCIE_INTR (INT_QUAD_BASE + 2)
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#define INT_PCIE_MSI (INT_QUAD_BASE + 3)
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#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4)
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#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5)
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#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6)
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#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7)
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#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8)
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#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9)
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#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10)
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#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11)
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#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12)
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#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13)
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#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14)
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#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15)
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#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16)
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#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17)
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#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18)
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#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19)
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#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20)
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#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21)
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#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22)
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#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23)
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#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24)
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#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25)
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#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26)
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#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27)
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#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28)
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#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29)
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#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
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#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
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#define INT_GPIO_BASE (INT_QUAD_BASE + 32)
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#define INT_GPIO_NR (28 * 8)
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#define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
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#endif
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34
arch/arm/mach-tegra/irq.c
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34
arch/arm/mach-tegra/irq.c
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@ -0,0 +1,34 @@
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/*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/gic.h>
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#include <mach/iomap.h>
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#include "board.h"
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void __init tegra_init_irq(void)
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{
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gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29);
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gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
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}
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