forked from luck/tmp_suning_uos_patched
Merge branch 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux
Pull i2c embedded fixes from Wolfram Sang: "The last bunch of (typical) i2c-embedded driver fixes for 3.6. Also update the MAINTAINERS file to point to my tree since people keep asking where to find their patches." * 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux: i2c: algo: pca: Fix mode selection for PCA9665 MAINTAINERS: fix tree for current i2c-embedded development i2c: mxs: correctly setup speed for non devicetree i2c: pnx: Fix read transactions of >= 2 bytes i2c: pnx: Fix bit definitions
This commit is contained in:
commit
5b799dde31
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@ -3388,7 +3388,7 @@ M: "Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de>
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L: linux-i2c@vger.kernel.org
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W: http://i2c.wiki.kernel.org/
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T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-i2c/
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T: git git://git.fluff.org/bjdooks/linux.git
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T: git git://git.pengutronix.de/git/wsa/linux.git
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S: Maintained
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F: Documentation/i2c/
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F: drivers/i2c/
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@ -476,17 +476,17 @@ static int pca_init(struct i2c_adapter *adap)
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/* To avoid integer overflow, use clock/100 for calculations */
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clock = pca_clock(pca_data) / 100;
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if (pca_data->i2c_clock > 10000) {
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if (pca_data->i2c_clock > 1000000) {
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mode = I2C_PCA_MODE_TURBO;
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min_tlow = 14;
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min_thi = 5;
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raise_fall_time = 22; /* Raise 11e-8s, Fall 11e-8s */
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} else if (pca_data->i2c_clock > 4000) {
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} else if (pca_data->i2c_clock > 400000) {
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mode = I2C_PCA_MODE_FASTP;
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min_tlow = 17;
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min_thi = 9;
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raise_fall_time = 22; /* Raise 11e-8s, Fall 11e-8s */
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} else if (pca_data->i2c_clock > 1000) {
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} else if (pca_data->i2c_clock > 100000) {
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mode = I2C_PCA_MODE_FAST;
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min_tlow = 44;
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min_thi = 20;
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@ -365,10 +365,6 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
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struct device_node *node = dev->of_node;
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int ret;
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if (!node)
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return -EINVAL;
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i2c->speed = &mxs_i2c_95kHz_config;
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ret = of_property_read_u32(node, "clock-frequency", &speed);
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if (ret)
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dev_warn(dev, "No I2C speed selected, using 100kHz\n");
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@ -419,10 +415,13 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
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return err;
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i2c->dev = dev;
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i2c->speed = &mxs_i2c_95kHz_config;
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err = mxs_i2c_get_ofdata(i2c);
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if (err)
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return err;
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if (dev->of_node) {
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err = mxs_i2c_get_ofdata(i2c);
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if (err)
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return err;
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}
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platform_set_drvdata(pdev, i2c);
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@ -48,8 +48,9 @@ enum {
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mcntrl_afie = 0x00000002,
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mcntrl_naie = 0x00000004,
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mcntrl_drmie = 0x00000008,
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mcntrl_daie = 0x00000020,
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mcntrl_rffie = 0x00000040,
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mcntrl_drsie = 0x00000010,
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mcntrl_rffie = 0x00000020,
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mcntrl_daie = 0x00000040,
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mcntrl_tffie = 0x00000080,
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mcntrl_reset = 0x00000100,
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mcntrl_cdbmode = 0x00000400,
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@ -290,31 +291,37 @@ static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
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* or we didn't 'ask' for it yet.
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*/
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if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
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dev_dbg(&alg_data->adapter.dev,
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"%s(): Write dummy data to fill Rx-fifo...\n",
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__func__);
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/* 'Asking' is done asynchronously, e.g. dummy TX of several
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* bytes is done before the first actual RX arrives in FIFO.
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* Therefore, ordered bytes (via TX) are counted separately.
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*/
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if (alg_data->mif.order) {
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dev_dbg(&alg_data->adapter.dev,
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"%s(): Write dummy data to fill Rx-fifo...\n",
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__func__);
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if (alg_data->mif.len == 1) {
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/* Last byte, do not acknowledge next rcv. */
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val |= stop_bit;
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if (alg_data->mif.order == 1) {
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/* Last byte, do not acknowledge next rcv. */
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val |= stop_bit;
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/*
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* Enable interrupt RFDAIE (data in Rx fifo),
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* and disable DRMIE (need data for Tx)
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*/
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ctl = ioread32(I2C_REG_CTL(alg_data));
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ctl |= mcntrl_rffie | mcntrl_daie;
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ctl &= ~mcntrl_drmie;
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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}
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/*
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* Enable interrupt RFDAIE (data in Rx fifo),
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* and disable DRMIE (need data for Tx)
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* Now we'll 'ask' for data:
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* For each byte we want to receive, we must
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* write a (dummy) byte to the Tx-FIFO.
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*/
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ctl = ioread32(I2C_REG_CTL(alg_data));
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ctl |= mcntrl_rffie | mcntrl_daie;
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ctl &= ~mcntrl_drmie;
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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iowrite32(val, I2C_REG_TX(alg_data));
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alg_data->mif.order--;
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}
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/*
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* Now we'll 'ask' for data:
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* For each byte we want to receive, we must
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* write a (dummy) byte to the Tx-FIFO.
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*/
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iowrite32(val, I2C_REG_TX(alg_data));
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return 0;
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}
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@ -514,6 +521,7 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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alg_data->mif.buf = pmsg->buf;
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alg_data->mif.len = pmsg->len;
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alg_data->mif.order = pmsg->len;
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alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
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I2C_SMBUS_READ : I2C_SMBUS_WRITE;
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alg_data->mif.ret = 0;
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@ -566,6 +574,7 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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/* Cleanup to be sure... */
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alg_data->mif.buf = NULL;
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alg_data->mif.len = 0;
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alg_data->mif.order = 0;
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dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
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__func__, ioread32(I2C_REG_STS(alg_data)));
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@ -22,6 +22,7 @@ struct i2c_pnx_mif {
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struct timer_list timer; /* Timeout */
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u8 * buf; /* Data buffer */
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int len; /* Length of data buffer */
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int order; /* RX Bytes to order via TX */
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};
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struct i2c_pnx_algo_data {
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