forked from luck/tmp_suning_uos_patched
ASoC: sglt5000: Fix SGTL5000_PLL_FRAC_DIV_MASK
SGTL5000_PLL_FRAC_DIV_MASK is used to mask bits 0-10 (11 bits in total) of register CHIP_PLL_CTRL, so fix the mask to accomodate all this bit range. Reported-by: Oskar Schirmer <oskar@scara.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> Cc: stable@vger.kernel.org
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@ -347,7 +347,7 @@
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#define SGTL5000_PLL_INT_DIV_MASK 0xf800
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#define SGTL5000_PLL_INT_DIV_SHIFT 11
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#define SGTL5000_PLL_INT_DIV_WIDTH 5
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#define SGTL5000_PLL_FRAC_DIV_MASK 0x0700
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#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff
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#define SGTL5000_PLL_FRAC_DIV_SHIFT 0
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#define SGTL5000_PLL_FRAC_DIV_WIDTH 11
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