forked from luck/tmp_suning_uos_patched
IB/mlx5: Mmap the HCA's clock info to user-space
This patch maps the new page to user space applications to allow converting a user space completion timestamp to system wall time at the lowest possible latency cost. By using a versioning scheme we allow compatibility between current and future userspace libraries. The change moves mlx5_ib_mmap_cmd enum from mlx5_ib.h to the abi header file mlx5-abi.h. Reviewed-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Yishai Hadas <yishaih@mellanox.com> Signed-off-by: Feras Daoud <ferasda@mellanox.com> Signed-off-by: Eitan Rabin <rabin@mellanox.com> Signed-off-by: Leon Romanovsky <leon@kernel.org> Signed-off-by: Doug Ledford <dledford@redhat.com>
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@ -1579,6 +1579,7 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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struct mlx5_ib_dev *dev = to_mdev(ibdev);
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struct mlx5_ib_alloc_ucontext_req_v2 req = {};
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struct mlx5_ib_alloc_ucontext_resp resp = {};
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struct mlx5_core_dev *mdev = dev->mdev;
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struct mlx5_ib_ucontext *context;
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struct mlx5_bfreg_info *bfregi;
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int ver;
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@ -1706,6 +1707,12 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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resp.response_length += sizeof(resp.eth_min_inline);
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}
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if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
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if (mdev->clock_info)
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resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
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resp.response_length += sizeof(resp.clock_info_versions);
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}
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/*
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* We don't want to expose information from the PCI bar that is located
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* after 4096 bytes, so if the arch only supports larger pages, let's
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@ -1719,8 +1726,7 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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resp.hca_core_clock_offset =
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offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
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}
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resp.response_length += sizeof(resp.hca_core_clock_offset) +
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sizeof(resp.reserved2);
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resp.response_length += sizeof(resp.hca_core_clock_offset);
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}
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if (field_avail(typeof(resp), log_uar_size, udata->outlen))
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@ -1959,6 +1965,38 @@ static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
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}
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}
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static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
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struct vm_area_struct *vma,
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struct mlx5_ib_ucontext *context)
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{
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phys_addr_t pfn;
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int err;
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if (vma->vm_end - vma->vm_start != PAGE_SIZE)
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return -EINVAL;
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if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
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return -EOPNOTSUPP;
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if (vma->vm_flags & VM_WRITE)
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return -EPERM;
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if (!dev->mdev->clock_info_page)
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return -EOPNOTSUPP;
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pfn = page_to_pfn(dev->mdev->clock_info_page);
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err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
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vma->vm_page_prot);
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if (err)
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return err;
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mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
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vma->vm_start,
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(unsigned long long)pfn << PAGE_SHIFT);
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return mlx5_ib_set_vma_data(vma, context);
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}
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static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
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struct vm_area_struct *vma,
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struct mlx5_ib_ucontext *context)
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@ -2121,6 +2159,8 @@ static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vm
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vma->vm_start,
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(unsigned long long)pfn << PAGE_SHIFT);
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break;
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case MLX5_IB_MMAP_CLOCK_INFO:
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return mlx5_ib_mmap_clock_info_page(dev, vma, context);
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default:
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return -EINVAL;
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@ -70,16 +70,6 @@ enum {
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MLX5_IB_MMAP_CMD_MASK = 0xff,
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};
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enum mlx5_ib_mmap_cmd {
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MLX5_IB_MMAP_REGULAR_PAGE = 0,
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MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
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MLX5_IB_MMAP_WC_PAGE = 2,
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MLX5_IB_MMAP_NC_PAGE = 3,
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/* 5 is chosen in order to be compatible with old versions of libmlx5 */
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MLX5_IB_MMAP_CORE_CLOCK = 5,
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MLX5_IB_MMAP_ALLOC_WC = 6,
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};
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enum {
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MLX5_RES_SCAT_DATA32_CQE = 0x1,
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MLX5_RES_SCAT_DATA64_CQE = 0x2,
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@ -124,7 +124,7 @@ struct mlx5_ib_alloc_ucontext_resp {
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__u8 cqe_version;
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__u8 cmds_supp_uhw;
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__u8 eth_min_inline;
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__u8 reserved2;
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__u8 clock_info_versions;
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__u64 hca_core_clock_offset;
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__u32 log_uar_size;
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__u32 num_uars_per_page;
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@ -394,7 +394,23 @@ struct mlx5_ib_clock_info {
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__u64 overflow_period;
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};
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enum mlx5_ib_mmap_cmd {
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MLX5_IB_MMAP_REGULAR_PAGE = 0,
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MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
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MLX5_IB_MMAP_WC_PAGE = 2,
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MLX5_IB_MMAP_NC_PAGE = 3,
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/* 5 is chosen in order to be compatible with old versions of libmlx5 */
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MLX5_IB_MMAP_CORE_CLOCK = 5,
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MLX5_IB_MMAP_ALLOC_WC = 6,
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MLX5_IB_MMAP_CLOCK_INFO = 7,
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};
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enum {
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MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
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};
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/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
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enum {
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MLX5_IB_CLOCK_INFO_V1 = 0,
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};
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#endif /* MLX5_ABI_USER_H */
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