forked from luck/tmp_suning_uos_patched
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: dmaengine: at_hdmac: fix buffer transfer size specification fsldma: fix issue of slow dma dmaengine i.MX SDMA: initialize on module_init dma : EG20T PCH: Fix miss-setting DMA descriptor intel_mid_dma: fix section mismatch warnings dmaengine: imx-sdma: fix bug in buffer descriptor initialization drivers/dma/ppc4xx: Use printf extension %pR for struct resource drivers/dma/ioat: Use the ccflag-y instead of EXTRA_CFLAGS drivers/dma/: Use the ccflag-y instead of EXTRA_CFLAGS dma: intel_mid_dma: fix double free on mid_setup_dma error path dma: imx-dma: fix imxdma_probe error path
This commit is contained in:
commit
5d43a1de26
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@ -1,8 +1,8 @@
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ifeq ($(CONFIG_DMADEVICES_DEBUG),y)
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EXTRA_CFLAGS += -DDEBUG
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ccflags-y += -DDEBUG
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endif
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ifeq ($(CONFIG_DMADEVICES_VDEBUG),y)
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EXTRA_CFLAGS += -DVERBOSE_DEBUG
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ccflags-y += -DVERBOSE_DEBUG
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endif
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obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
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@ -722,7 +722,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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desc->lli.daddr = mem;
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desc->lli.ctrla = ctrla
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| ATC_DST_WIDTH(mem_width)
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| len >> mem_width;
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| len >> reg_width;
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desc->lli.ctrlb = ctrlb;
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if (!first) {
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@ -50,9 +50,11 @@ static void dma_init(struct fsldma_chan *chan)
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* EIE - Error interrupt enable
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* EOSIE - End of segments interrupt enable (basic mode)
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* EOLNIE - End of links interrupt enable
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* BWC - Bandwidth sharing among channels
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*/
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
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| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
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| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
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| FSL_DMA_MR_EOSIE, 32);
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break;
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case FSL_DMA_IP_83XX:
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/* Set the channel to below modes:
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author:
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* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
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@ -36,6 +36,13 @@
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#define FSL_DMA_MR_DAHE 0x00002000
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#define FSL_DMA_MR_SAHE 0x00001000
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/*
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* Bandwidth/pause control determines how many bytes a given
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* channel is allowed to transfer before the DMA engine pauses
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* the current channel and switches to the next channel
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*/
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#define FSL_DMA_MR_BWC 0x08000000
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/* Special MR definition for MPC8349 */
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#define FSL_DMA_MR_EOTIE 0x00000080
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#define FSL_DMA_MR_PRC_RM 0x00000800
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@ -379,7 +379,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
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return 0;
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err_init:
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while (i-- >= 0) {
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while (--i >= 0) {
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struct imxdma_channel *imxdmac = &imxdma->channel[i];
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imx_dma_free(imxdmac->imxdma_channel);
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}
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@ -951,7 +951,7 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
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int param;
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bd->buffer_addr = sgl->dma_address;
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bd->buffer_addr = sg->dma_address;
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count = sg->length;
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@ -1385,7 +1385,7 @@ static int __init sdma_module_init(void)
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{
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return platform_driver_probe(&sdma_driver, sdma_probe);
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}
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subsys_initcall(sdma_module_init);
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module_init(sdma_module_init);
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MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
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MODULE_DESCRIPTION("i.MX SDMA driver");
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@ -1075,7 +1075,6 @@ static int mid_setup_dma(struct pci_dev *pdev)
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if (NULL == dma->dma_pool) {
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pr_err("ERR_MDMA:pci_pool_create failed\n");
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err = -ENOMEM;
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kfree(dma);
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goto err_dma_pool;
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}
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@ -1186,7 +1185,6 @@ static int mid_setup_dma(struct pci_dev *pdev)
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free_irq(pdev->irq, dma);
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err_irq:
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pci_pool_destroy(dma->dma_pool);
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kfree(dma);
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err_dma_pool:
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pr_err("ERR_MDMA:setup_dma failed: %d\n", err);
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return err;
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@ -1413,7 +1411,7 @@ static const struct dev_pm_ops intel_mid_dma_pm = {
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.runtime_idle = dma_runtime_idle,
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};
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static struct pci_driver intel_mid_dma_pci = {
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static struct pci_driver intel_mid_dma_pci_driver = {
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.name = "Intel MID DMA",
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.id_table = intel_mid_dma_ids,
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.probe = intel_mid_dma_probe,
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@ -1431,13 +1429,13 @@ static int __init intel_mid_dma_init(void)
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{
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pr_debug("INFO_MDMA: LNW DMA Driver Version %s\n",
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INTEL_MID_DMA_DRIVER_VERSION);
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return pci_register_driver(&intel_mid_dma_pci);
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return pci_register_driver(&intel_mid_dma_pci_driver);
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}
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fs_initcall(intel_mid_dma_init);
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static void __exit intel_mid_dma_exit(void)
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{
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pci_unregister_driver(&intel_mid_dma_pci);
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pci_unregister_driver(&intel_mid_dma_pci_driver);
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}
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module_exit(intel_mid_dma_exit);
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@ -1,2 +1,2 @@
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obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
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ioatdma-objs := pci.o dma.o dma_v2.o dma_v3.o dca.o
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ioatdma-y := pci.o dma.o dma_v2.o dma_v3.o dca.o
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@ -259,11 +259,6 @@ static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
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return;
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}
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channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
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channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
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channel_writel(pd_chan, SIZE, desc->regs.size);
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channel_writel(pd_chan, NEXT, desc->regs.next);
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dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
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pd_chan->chan.chan_id, desc->regs.dev_addr);
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dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
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dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
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pd_chan->chan.chan_id, desc->regs.next);
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if (list_empty(&desc->tx_list))
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if (list_empty(&desc->tx_list)) {
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channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
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channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
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channel_writel(pd_chan, SIZE, desc->regs.size);
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channel_writel(pd_chan, NEXT, desc->regs.next);
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pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
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else
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} else {
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channel_writel(pd_chan, NEXT, desc->txd.phys);
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pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
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}
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val = dma_readl(pd, CTL2);
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val |= 1 << (DMA_CTL2_START_SHIFT_BITS + pd_chan->chan.chan_id);
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@ -4449,9 +4449,8 @@ static int __devinit ppc440spe_adma_probe(struct platform_device *ofdev,
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if (!request_mem_region(res.start, resource_size(&res),
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dev_driver_string(&ofdev->dev))) {
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dev_err(&ofdev->dev, "failed to request memory region "
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"(0x%016llx-0x%016llx)\n",
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(u64)res.start, (u64)res.end);
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dev_err(&ofdev->dev, "failed to request memory region %pR\n",
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&res);
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initcode = PPC_ADMA_INIT_MEMREG;
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ret = -EBUSY;
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goto out;
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