forked from luck/tmp_suning_uos_patched
iommu/vt-d: Fix SVM IOTLB flush handling
Change the 'pages' parameter to 'unsigned long' to avoid overflow. Fix the device-IOTLB flush parameter calculation — the size of the IOTLB flush is indicated by the position of the least significant zero bit in the address field. For example, a value of 0x12345f000 will flush from 0x123440000 to 0x12347ffff (256KiB). Finally, the cap_pgsel_inv() is not relevant to SVM; the spec says that *all* implementations must support page-selective invaliation for "first-level" translations. So don't check for it. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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5d52f482eb
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@ -147,13 +147,11 @@ int intel_svm_finish_prq(struct intel_iommu *iommu)
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}
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static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
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unsigned long address, int pages, int ih, int gl)
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unsigned long address, unsigned long pages, int ih, int gl)
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{
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struct qi_desc desc;
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int mask = ilog2(__roundup_pow_of_two(pages));
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if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap) ||
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mask > cap_max_amask_val(svm->iommu->cap)) {
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if (pages == -1) {
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/* For global kernel pages we have to flush them in *all* PASIDs
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* because that's the only option the hardware gives us. Despite
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* the fact that they are actually only accessible through one. */
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@ -165,31 +163,28 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
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QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
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desc.high = 0;
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} else {
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int mask = ilog2(__roundup_pow_of_two(pages));
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desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
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QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
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desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
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QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
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}
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qi_submit_sync(&desc, svm->iommu);
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if (sdev->dev_iotlb) {
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desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
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QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
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if (mask) {
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unsigned long adr, delta;
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if (pages == -1) {
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desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
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} else if (pages > 1) {
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/* The least significant zero bit indicates the size. So,
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* for example, an "address" value of 0x12345f000 will
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* flush from 0x123440000 to 0x12347ffff (256KiB). */
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unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
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unsigned long mask = __rounddown_pow_of_two(address ^ last);;
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/* Least significant zero bits in the address indicate the
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* range of the request. So mask them out according to the
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* size. */
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adr = address & ((1<<(VTD_PAGE_SHIFT + mask)) - 1);
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/* Now ensure that we round down further if the original
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* request was not aligned w.r.t. its size */
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delta = address - adr;
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if (delta + (pages << VTD_PAGE_SHIFT) >= (1 << (VTD_PAGE_SHIFT + mask)))
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adr &= ~(1 << (VTD_PAGE_SHIFT + mask));
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desc.high = QI_DEV_EIOTLB_ADDR(adr) | QI_DEV_EIOTLB_SIZE;
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desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
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} else {
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desc.high = QI_DEV_EIOTLB_ADDR(address);
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}
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@ -198,7 +193,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
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}
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static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
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int pages, int ih, int gl)
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unsigned long pages, int ih, int gl)
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{
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struct intel_svm_dev *sdev;
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