forked from luck/tmp_suning_uos_patched
fm10k: Reset mailbox global interrupts
When a data path reset is initiated, write control to the PCIE_GMBX is yanked from the switch manager. The switch manager writes to this register to clear mailbox global interrupt bits as part of its mailbox interrupt handling routine. When the device recovers from the data path reset and these bits are not cleared, it will prevent future mailbox global interrupts from being triggered. Upon confirming that the device has exited from a data path reset, clear these bits to ensure the proper functioning of the mailbox global interrupt. Signed-off-by: Ngai-Mint Kwan <ngai-mint.kwan@intel.com> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Krishneil Singh <Krishneil.k.singh@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -41,6 +41,8 @@ struct fm10k_mbx_info;
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#define FM10K_MBX_ACK_INTERRUPT 0x00000010
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#define FM10K_MBX_INTERRUPT_ENABLE 0x00000020
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#define FM10K_MBX_INTERRUPT_DISABLE 0x00000040
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#define FM10K_MBX_GLOBAL_REQ_INTERRUPT 0x00000200
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#define FM10K_MBX_GLOBAL_ACK_INTERRUPT 0x00000400
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#define FM10K_MBICR(_n) ((_n) + 0x18840)
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#define FM10K_GMBX 0x18842
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@ -77,6 +77,10 @@ static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
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if (!(reg & FM10K_IP_NOTINRESET))
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err = FM10K_ERR_RESET_FAILED;
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/* Reset mailbox global interrupts */
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reg = FM10K_MBX_GLOBAL_REQ_INTERRUPT | FM10K_MBX_GLOBAL_ACK_INTERRUPT;
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fm10k_write_reg(hw, FM10K_GMBX, reg);
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out:
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return err;
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}
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