forked from luck/tmp_suning_uos_patched
Our usual PR for the Allwinner SoCs, this time adding support for the
Allwinner A100 SoC, and adding support for the sigma-delta modulation on the audio PLL for the R40. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCX2jMHwAKCRDj7w1vZxhR xRFUAQDnGPaCxG4aQL5C9OuEM95xS5mvqh1nHqXEpzTL27YrMgEA56BkffQDTs7T +opPbuCVil5UIlZodc8CpJFpUkG3QQ4= =DF1k -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Maxime Ripard: Our usual PR for the Allwinner SoCs, this time adding support for the Allwinner A100 SoC, and adding support for the sigma-delta modulation on the audio PLL for the R40. * tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL clk: sunxi-ng: add support for the Allwinner A100 CCU dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
This commit is contained in:
Stephen Boyd
commit
5eefe5e183
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@ -36,6 +36,8 @@ properties:
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- allwinner,sun9i-a80-ccu
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- allwinner,sun50i-a64-ccu
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- allwinner,sun50i-a64-r-ccu
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- allwinner,sun50i-a100-ccu
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- allwinner,sun50i-a100-r-ccu
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- allwinner,sun50i-h5-ccu
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- allwinner,sun50i-h6-ccu
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- allwinner,sun50i-h6-r-ccu
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@ -78,6 +80,7 @@ if:
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- allwinner,sun8i-a83t-r-ccu
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- allwinner,sun8i-h3-r-ccu
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- allwinner,sun50i-a64-r-ccu
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- allwinner,sun50i-a100-r-ccu
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- allwinner,sun50i-h6-r-ccu
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then:
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@ -94,7 +97,9 @@ else:
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if:
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properties:
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compatible:
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const: allwinner,sun50i-h6-ccu
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enum:
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- allwinner,sun50i-a100-ccu
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- allwinner,sun50i-h6-ccu
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then:
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properties:
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@ -17,6 +17,16 @@ config SUN50I_A64_CCU
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default ARM64 && ARCH_SUNXI
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depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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config SUN50I_A100_CCU
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bool "Support for the Allwinner A100 CCU"
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default ARM64 && ARCH_SUNXI
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depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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config SUN50I_A100_R_CCU
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bool "Support for the Allwinner A100 PRCM CCU"
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default ARM64 && ARCH_SUNXI
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depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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config SUN50I_H6_CCU
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bool "Support for the Allwinner H6 CCU"
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default ARM64 && ARCH_SUNXI
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@ -23,6 +23,8 @@ obj-y += ccu_mp.o
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# SoC support
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obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
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obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
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obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
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obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
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obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
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obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
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obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
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214
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
Normal file
214
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
Normal file
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@ -0,0 +1,214 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu_nm.h"
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#include "ccu-sun50i-a100-r.h"
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static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
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"iosc", "pll-periph0" };
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static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
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{ .index = 3, .shift = 0, .width = 5 },
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};
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static struct ccu_div r_cpus_clk = {
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.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
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.mux = {
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.shift = 24,
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.width = 2,
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.var_predivs = cpus_r_apb2_predivs,
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.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
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},
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.common = {
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.reg = 0x000,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS("cpus",
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cpus_r_apb2_parents,
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&ccu_div_ops,
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0),
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},
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};
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static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
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static struct ccu_div r_apb1_clk = {
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.div = _SUNXI_CCU_DIV(0, 2),
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.common = {
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.reg = 0x00c,
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.hw.init = CLK_HW_INIT("r-apb1",
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"r-ahb",
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&ccu_div_ops,
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0),
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},
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};
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static struct ccu_div r_apb2_clk = {
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.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
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.mux = {
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.shift = 24,
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.width = 2,
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.var_predivs = cpus_r_apb2_predivs,
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.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
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},
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.common = {
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.reg = 0x010,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS("r-apb2",
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cpus_r_apb2_parents,
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&ccu_div_ops,
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0),
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},
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};
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static const struct clk_parent_data clk_parent_r_apb1[] = {
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{ .hw = &r_apb1_clk.common.hw },
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};
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static const struct clk_parent_data clk_parent_r_apb2[] = {
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{ .hw = &r_apb2_clk.common.hw },
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};
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static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
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0x11c, BIT(0), 0);
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static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
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0x12c, BIT(0), 0);
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static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
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"iosc" };
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static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents,
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0x130, 24, 2, 0);
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static SUNXI_CCU_GATE_DATA(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm",
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clk_parent_r_apb1, 0x13c, BIT(0), 0);
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static SUNXI_CCU_GATE_DATA(r_apb1_ppu_clk, "r-apb1-ppu", clk_parent_r_apb1,
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0x17c, BIT(0), 0);
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static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2,
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0x18c, BIT(0), 0);
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static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2,
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0x19c, BIT(0), 0);
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static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2,
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0x19c, BIT(1), 0);
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static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };
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static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",
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r_apb1_ir_rx_parents, 0x1c0,
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0, 5, /* M */
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8, 2, /* P */
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24, 1, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_GATE_DATA(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx",
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clk_parent_r_apb1, 0x1cc, BIT(0), 0);
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static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
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0x20c, BIT(0), 0);
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static struct ccu_common *sun50i_a100_r_ccu_clks[] = {
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&r_cpus_clk.common,
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&r_apb1_clk.common,
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&r_apb2_clk.common,
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&r_apb1_timer_clk.common,
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&r_apb1_twd_clk.common,
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&r_apb1_pwm_clk.common,
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&r_apb1_bus_pwm_clk.common,
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&r_apb1_ppu_clk.common,
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&r_apb2_uart_clk.common,
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&r_apb2_i2c0_clk.common,
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&r_apb2_i2c1_clk.common,
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&r_apb1_ir_rx_clk.common,
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&r_apb1_bus_ir_rx_clk.common,
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&r_ahb_bus_rtc_clk.common,
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};
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static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
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.hws = {
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[CLK_R_CPUS] = &r_cpus_clk.common.hw,
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[CLK_R_AHB] = &r_ahb_clk.hw,
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[CLK_R_APB1] = &r_apb1_clk.common.hw,
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[CLK_R_APB2] = &r_apb2_clk.common.hw,
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[CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
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[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
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[CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
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[CLK_R_APB1_BUS_PWM] = &r_apb1_bus_pwm_clk.common.hw,
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[CLK_R_APB1_PPU] = &r_apb1_ppu_clk.common.hw,
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[CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
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[CLK_R_APB2_I2C0] = &r_apb2_i2c0_clk.common.hw,
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[CLK_R_APB2_I2C1] = &r_apb2_i2c1_clk.common.hw,
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[CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw,
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[CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw,
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[CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
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[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
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[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
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[RST_R_APB1_PPU] = { 0x17c, BIT(16) },
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[RST_R_APB2_UART] = { 0x18c, BIT(16) },
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[RST_R_APB2_I2C0] = { 0x19c, BIT(16) },
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[RST_R_APB2_I2C1] = { 0x19c, BIT(17) },
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[RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) },
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[RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
|
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};
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|
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static const struct sunxi_ccu_desc sun50i_a100_r_ccu_desc = {
|
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.ccu_clks = sun50i_a100_r_ccu_clks,
|
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.num_ccu_clks = ARRAY_SIZE(sun50i_a100_r_ccu_clks),
|
||||
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.hw_clks = &sun50i_a100_r_hw_clks,
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||||
|
||||
.resets = sun50i_a100_r_ccu_resets,
|
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.num_resets = ARRAY_SIZE(sun50i_a100_r_ccu_resets),
|
||||
};
|
||||
|
||||
static int sun50i_a100_r_ccu_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *reg;
|
||||
|
||||
reg = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(reg))
|
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return PTR_ERR(reg);
|
||||
|
||||
return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a100_r_ccu_desc);
|
||||
}
|
||||
|
||||
static const struct of_device_id sun50i_a100_r_ccu_ids[] = {
|
||||
{ .compatible = "allwinner,sun50i-a100-r-ccu" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver sun50i_a100_r_ccu_driver = {
|
||||
.probe = sun50i_a100_r_ccu_probe,
|
||||
.driver = {
|
||||
.name = "sun50i-a100-r-ccu",
|
||||
.of_match_table = sun50i_a100_r_ccu_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun50i_a100_r_ccu_driver);
|
||||
21
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
Normal file
21
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUN50I_A100_R_H
|
||||
#define _CCU_SUN50I_A100_R_H
|
||||
|
||||
#include <dt-bindings/clock/sun50i-a100-r-ccu.h>
|
||||
#include <dt-bindings/reset/sun50i-a100-r-ccu.h>
|
||||
|
||||
#define CLK_R_CPUS 0
|
||||
#define CLK_R_AHB 1
|
||||
|
||||
/* exported except APB1 for R_PIO */
|
||||
|
||||
#define CLK_R_APB2 3
|
||||
|
||||
#define CLK_NUMBER (CLK_R_AHB_BUS_RTC + 1)
|
||||
|
||||
#endif /* _CCU_SUN50I_A100_R_H */
|
||||
1276
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
Normal file
1276
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
Normal file
File diff suppressed because it is too large
Load Diff
56
drivers/clk/sunxi-ng/ccu-sun50i-a100.h
Normal file
56
drivers/clk/sunxi-ng/ccu-sun50i-a100.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUN50I_A100_H_
|
||||
#define _CCU_SUN50I_A100_H_
|
||||
|
||||
#include <dt-bindings/clock/sun50i-a100-ccu.h>
|
||||
#include <dt-bindings/reset/sun50i-a100-ccu.h>
|
||||
|
||||
#define CLK_OSC12M 0
|
||||
#define CLK_PLL_CPUX 1
|
||||
#define CLK_PLL_DDR0 2
|
||||
|
||||
/* PLL_PERIPH0 exported for PRCM */
|
||||
|
||||
#define CLK_PLL_PERIPH0_2X 4
|
||||
#define CLK_PLL_PERIPH1 5
|
||||
#define CLK_PLL_PERIPH1_2X 6
|
||||
#define CLK_PLL_GPU 7
|
||||
#define CLK_PLL_VIDEO0 8
|
||||
#define CLK_PLL_VIDEO0_2X 9
|
||||
#define CLK_PLL_VIDEO0_4X 10
|
||||
#define CLK_PLL_VIDEO1 11
|
||||
#define CLK_PLL_VIDEO1_2X 12
|
||||
#define CLK_PLL_VIDEO1_4X 13
|
||||
#define CLK_PLL_VIDEO2 14
|
||||
#define CLK_PLL_VIDEO2_2X 15
|
||||
#define CLK_PLL_VIDEO2_4X 16
|
||||
#define CLK_PLL_VIDEO3 17
|
||||
#define CLK_PLL_VIDEO3_2X 18
|
||||
#define CLK_PLL_VIDEO3_4X 19
|
||||
#define CLK_PLL_VE 20
|
||||
#define CLK_PLL_COM 21
|
||||
#define CLK_PLL_COM_AUDIO 22
|
||||
#define CLK_PLL_AUDIO 23
|
||||
|
||||
/* CPUX clock exported for DVFS */
|
||||
|
||||
#define CLK_AXI 25
|
||||
#define CLK_CPUX_APB 26
|
||||
#define CLK_PSI_AHB1_AHB2 27
|
||||
#define CLK_AHB3 28
|
||||
|
||||
/* APB1 clock exported for PIO */
|
||||
|
||||
#define CLK_APB2 30
|
||||
|
||||
/* All module clocks and bus gates are exported except DRAM */
|
||||
|
||||
#define CLK_BUS_DRAM 58
|
||||
|
||||
#define CLK_NUMBER (CLK_CSI_ISP + 1)
|
||||
|
||||
#endif /* _CCU_SUN50I_A100_H_ */
|
||||
|
|
@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = {
|
|||
* the base (2x, 4x and 8x), and one variable divider (the one true
|
||||
* pll audio).
|
||||
*
|
||||
* We don't have any need for the variable divider for now, so we just
|
||||
* hardcode it to match with the clock names
|
||||
* With sigma-delta modulation for fractional-N on the audio PLL,
|
||||
* we have to use specific dividers. This means the variable divider
|
||||
* can no longer be used, as the audio codec requests the exact clock
|
||||
* rates we support through this mechanism. So we now hard code the
|
||||
* variable divider to 1. This means the clock rates will no longer
|
||||
* match the clock names.
|
||||
*/
|
||||
#define SUN8I_R40_PLL_AUDIO_REG 0x008
|
||||
|
||||
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
||||
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
|
||||
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
|
||||
};
|
||||
|
||||
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||
"osc24M", 0x008,
|
||||
8, 7, /* N */
|
||||
0, 5, /* M */
|
||||
pll_audio_sdm_table, BIT(24),
|
||||
0x284, BIT(31),
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
|
||||
"osc24M", 0x0010,
|
||||
|
|
@ -952,10 +963,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
|
|||
&pll_audio_base_clk.common.hw
|
||||
};
|
||||
|
||||
/* We hardcode the divider to 4 for now */
|
||||
/* We hardcode the divider to 1 for now */
|
||||
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
|
||||
clk_parent_pll_audio,
|
||||
4, 1, CLK_SET_RATE_PARENT);
|
||||
1, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
|
||||
clk_parent_pll_audio,
|
||||
2, 1, CLK_SET_RATE_PARENT);
|
||||
|
|
@ -1307,10 +1318,10 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(reg))
|
||||
return PTR_ERR(reg);
|
||||
|
||||
/* Force the PLL-Audio-1x divider to 4 */
|
||||
/* Force the PLL-Audio-1x divider to 1 */
|
||||
val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||
val &= ~GENMASK(19, 16);
|
||||
writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||
writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||
|
||||
/* Force PLL-MIPI to MIPI mode */
|
||||
val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
|
||||
|
|
|
|||
116
include/dt-bindings/clock/sun50i-a100-ccu.h
Normal file
116
include/dt-bindings/clock/sun50i-a100-ccu.h
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_A100_H_
|
||||
|
||||
#define CLK_PLL_PERIPH0 3
|
||||
|
||||
#define CLK_CPUX 24
|
||||
|
||||
#define CLK_APB1 29
|
||||
|
||||
#define CLK_MBUS 31
|
||||
#define CLK_DE 32
|
||||
#define CLK_BUS_DE 33
|
||||
#define CLK_G2D 34
|
||||
#define CLK_BUS_G2D 35
|
||||
#define CLK_GPU 36
|
||||
#define CLK_BUS_GPU 37
|
||||
#define CLK_CE 38
|
||||
#define CLK_BUS_CE 39
|
||||
#define CLK_VE 40
|
||||
#define CLK_BUS_VE 41
|
||||
#define CLK_BUS_DMA 42
|
||||
#define CLK_BUS_MSGBOX 43
|
||||
#define CLK_BUS_SPINLOCK 44
|
||||
#define CLK_BUS_HSTIMER 45
|
||||
#define CLK_AVS 46
|
||||
#define CLK_BUS_DBG 47
|
||||
#define CLK_BUS_PSI 48
|
||||
#define CLK_BUS_PWM 49
|
||||
#define CLK_BUS_IOMMU 50
|
||||
#define CLK_MBUS_DMA 51
|
||||
#define CLK_MBUS_VE 52
|
||||
#define CLK_MBUS_CE 53
|
||||
#define CLK_MBUS_NAND 54
|
||||
#define CLK_MBUS_CSI 55
|
||||
#define CLK_MBUS_ISP 56
|
||||
#define CLK_MBUS_G2D 57
|
||||
|
||||
#define CLK_NAND0 59
|
||||
#define CLK_NAND1 60
|
||||
#define CLK_BUS_NAND 61
|
||||
#define CLK_MMC0 62
|
||||
#define CLK_MMC1 63
|
||||
#define CLK_MMC2 64
|
||||
#define CLK_MMC3 65
|
||||
#define CLK_BUS_MMC0 66
|
||||
#define CLK_BUS_MMC1 67
|
||||
#define CLK_BUS_MMC2 68
|
||||
#define CLK_BUS_UART0 69
|
||||
#define CLK_BUS_UART1 70
|
||||
#define CLK_BUS_UART2 71
|
||||
#define CLK_BUS_UART3 72
|
||||
#define CLK_BUS_UART4 73
|
||||
#define CLK_BUS_I2C0 74
|
||||
#define CLK_BUS_I2C1 75
|
||||
#define CLK_BUS_I2C2 76
|
||||
#define CLK_BUS_I2C3 77
|
||||
#define CLK_SPI0 78
|
||||
#define CLK_SPI1 79
|
||||
#define CLK_SPI2 80
|
||||
#define CLK_BUS_SPI0 81
|
||||
#define CLK_BUS_SPI1 82
|
||||
#define CLK_BUS_SPI2 83
|
||||
#define CLK_EMAC_25M 84
|
||||
#define CLK_BUS_EMAC 85
|
||||
#define CLK_IR_RX 86
|
||||
#define CLK_BUS_IR_RX 87
|
||||
#define CLK_IR_TX 88
|
||||
#define CLK_BUS_IR_TX 89
|
||||
#define CLK_BUS_GPADC 90
|
||||
#define CLK_BUS_THS 91
|
||||
#define CLK_I2S0 92
|
||||
#define CLK_I2S1 93
|
||||
#define CLK_I2S2 94
|
||||
#define CLK_I2S3 95
|
||||
#define CLK_BUS_I2S0 96
|
||||
#define CLK_BUS_I2S1 97
|
||||
#define CLK_BUS_I2S2 98
|
||||
#define CLK_BUS_I2S3 99
|
||||
#define CLK_SPDIF 100
|
||||
#define CLK_BUS_SPDIF 101
|
||||
#define CLK_DMIC 102
|
||||
#define CLK_BUS_DMIC 103
|
||||
#define CLK_AUDIO_DAC 104
|
||||
#define CLK_AUDIO_ADC 105
|
||||
#define CLK_AUDIO_4X 106
|
||||
#define CLK_BUS_AUDIO_CODEC 107
|
||||
#define CLK_USB_OHCI0 108
|
||||
#define CLK_USB_PHY0 109
|
||||
#define CLK_USB_OHCI1 110
|
||||
#define CLK_USB_PHY1 111
|
||||
#define CLK_BUS_OHCI0 112
|
||||
#define CLK_BUS_OHCI1 113
|
||||
#define CLK_BUS_EHCI0 114
|
||||
#define CLK_BUS_EHCI1 115
|
||||
#define CLK_BUS_OTG 116
|
||||
#define CLK_BUS_LRADC 117
|
||||
#define CLK_BUS_DPSS_TOP0 118
|
||||
#define CLK_BUS_DPSS_TOP1 119
|
||||
#define CLK_MIPI_DSI 120
|
||||
#define CLK_BUS_MIPI_DSI 121
|
||||
#define CLK_TCON_LCD 122
|
||||
#define CLK_BUS_TCON_LCD 123
|
||||
#define CLK_LEDC 124
|
||||
#define CLK_BUS_LEDC 125
|
||||
#define CLK_CSI_TOP 126
|
||||
#define CLK_CSI0_MCLK 127
|
||||
#define CLK_CSI1_MCLK 128
|
||||
#define CLK_BUS_CSI 129
|
||||
#define CLK_CSI_ISP 130
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */
|
||||
23
include/dt-bindings/clock/sun50i-a100-r-ccu.h
Normal file
23
include/dt-bindings/clock/sun50i-a100-r-ccu.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
|
||||
|
||||
#define CLK_R_APB1 2
|
||||
|
||||
#define CLK_R_APB1_TIMER 4
|
||||
#define CLK_R_APB1_TWD 5
|
||||
#define CLK_R_APB1_PWM 6
|
||||
#define CLK_R_APB1_BUS_PWM 7
|
||||
#define CLK_R_APB1_PPU 8
|
||||
#define CLK_R_APB2_UART 9
|
||||
#define CLK_R_APB2_I2C0 10
|
||||
#define CLK_R_APB2_I2C1 11
|
||||
#define CLK_R_APB1_IR 12
|
||||
#define CLK_R_APB1_BUS_IR 13
|
||||
#define CLK_R_AHB_BUS_RTC 14
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */
|
||||
68
include/dt-bindings/reset/sun50i-a100-ccu.h
Normal file
68
include/dt-bindings/reset/sun50i-a100-ccu.h
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_
|
||||
#define _DT_BINDINGS_RESET_SUN50I_A100_H_
|
||||
|
||||
#define RST_MBUS 0
|
||||
#define RST_BUS_DE 1
|
||||
#define RST_BUS_G2D 2
|
||||
#define RST_BUS_GPU 3
|
||||
#define RST_BUS_CE 4
|
||||
#define RST_BUS_VE 5
|
||||
#define RST_BUS_DMA 6
|
||||
#define RST_BUS_MSGBOX 7
|
||||
#define RST_BUS_SPINLOCK 8
|
||||
#define RST_BUS_HSTIMER 9
|
||||
#define RST_BUS_DBG 10
|
||||
#define RST_BUS_PSI 11
|
||||
#define RST_BUS_PWM 12
|
||||
#define RST_BUS_DRAM 13
|
||||
#define RST_BUS_NAND 14
|
||||
#define RST_BUS_MMC0 15
|
||||
#define RST_BUS_MMC1 16
|
||||
#define RST_BUS_MMC2 17
|
||||
#define RST_BUS_UART0 18
|
||||
#define RST_BUS_UART1 19
|
||||
#define RST_BUS_UART2 20
|
||||
#define RST_BUS_UART3 21
|
||||
#define RST_BUS_UART4 22
|
||||
#define RST_BUS_I2C0 23
|
||||
#define RST_BUS_I2C1 24
|
||||
#define RST_BUS_I2C2 25
|
||||
#define RST_BUS_I2C3 26
|
||||
#define RST_BUS_SPI0 27
|
||||
#define RST_BUS_SPI1 28
|
||||
#define RST_BUS_SPI2 29
|
||||
#define RST_BUS_EMAC 30
|
||||
#define RST_BUS_IR_RX 31
|
||||
#define RST_BUS_IR_TX 32
|
||||
#define RST_BUS_GPADC 33
|
||||
#define RST_BUS_THS 34
|
||||
#define RST_BUS_I2S0 35
|
||||
#define RST_BUS_I2S1 36
|
||||
#define RST_BUS_I2S2 37
|
||||
#define RST_BUS_I2S3 38
|
||||
#define RST_BUS_SPDIF 39
|
||||
#define RST_BUS_DMIC 40
|
||||
#define RST_BUS_AUDIO_CODEC 41
|
||||
#define RST_USB_PHY0 42
|
||||
#define RST_USB_PHY1 43
|
||||
#define RST_BUS_OHCI0 44
|
||||
#define RST_BUS_OHCI1 45
|
||||
#define RST_BUS_EHCI0 46
|
||||
#define RST_BUS_EHCI1 47
|
||||
#define RST_BUS_OTG 48
|
||||
#define RST_BUS_LRADC 49
|
||||
#define RST_BUS_DPSS_TOP0 50
|
||||
#define RST_BUS_DPSS_TOP1 51
|
||||
#define RST_BUS_MIPI_DSI 52
|
||||
#define RST_BUS_TCON_LCD 53
|
||||
#define RST_BUS_LVDS 54
|
||||
#define RST_BUS_LEDC 55
|
||||
#define RST_BUS_CSI 56
|
||||
#define RST_BUS_CSI_ISP 57
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */
|
||||
18
include/dt-bindings/reset/sun50i-a100-r-ccu.h
Normal file
18
include/dt-bindings/reset/sun50i-a100-r-ccu.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_
|
||||
#define _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_
|
||||
|
||||
#define RST_R_APB1_TIMER 0
|
||||
#define RST_R_APB1_BUS_PWM 1
|
||||
#define RST_R_APB1_PPU 2
|
||||
#define RST_R_APB2_UART 3
|
||||
#define RST_R_APB2_I2C0 4
|
||||
#define RST_R_APB2_I2C1 5
|
||||
#define RST_R_APB1_BUS_IR 6
|
||||
#define RST_R_AHB_BUS_RTC 7
|
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ */
|
||||
Loading…
Reference in New Issue
Block a user