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i7core_edac: Fix ecc enable shift

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From: Keith Mannthey <kmannth@us.ibm.com>

Simple correction to a shift value.
ECC_ENABLED is bit 4 of MC_STATUS, Dev 3 Fun 0 Offset 0x4c

This correctly identifies the state of the ECC at the machine.

Signed-off-by: Keith Mannthey <kmannth@us.ibm.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Keith Mannthey 2009-09-02 23:46:59 -03:00 committed by Mauro Carvalho Chehab
parent 3ef288a983
commit 61053fdedb
1 changed files with 1 additions and 1 deletions
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drivers/edac/i7core_edac.c
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@ -286,7 +286,7 @@ static struct edac_pci_ctl_info *i7core_pci;
#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
/* MC_STATUS bits */
#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 3))
#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
/* MC_MAX_DOD read functions */