AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

spi: spi-ep93xx: fix wrong SPI mode selection

Browse Source 
The mode bits on control register 0 are in a different order compared
to the spi mode define values. Thus, in the current code, it fails to
set the correct SPI mode selection. Fix it.

Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Link: https://lore.kernel.org/r/20200402121022.9976-1-js07.lee@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jungseung Lee 2020-04-02 21:10:22 +09:00 committed by Mark Brown
parent ebb3b9a92b
commit 61249ce08e
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/spi/spi-ep93xx.c
View File

@ -31,7 +31,8 @@
#include <linux/platform_data/spi-ep93xx.h>
#define SSPCR0 0x0000
#define SSPCR0_MODE_SHIFT 6
#define SSPCR0_SPO BIT(6)
#define SSPCR0_SPH BIT(7)
#define SSPCR0_SCR_SHIFT 8
#define SSPCR1 0x0004
@ -159,7 +160,10 @@ static int ep93xx_spi_chip_setup(struct spi_master *master,
return err;
cr0 = div_scr << SSPCR0_SCR_SHIFT;
cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT;
if (spi->mode & SPI_CPOL)
cr0 |= SSPCR0_SPO;
if (spi->mode & SPI_CPHA)
cr0 |= SSPCR0_SPH;
cr0 |= dss;
dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",