forked from luck/tmp_suning_uos_patched
Merge branch 'fixes' into next
There's a few important fixes in our fixes branch, in particular the pgd/pud_present() one, so merge it now.
This commit is contained in:
commit
637cfeb9f9
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@ -904,7 +904,7 @@ static inline int pud_none(pud_t pud)
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static inline int pud_present(pud_t pud)
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{
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return (pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
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return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
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}
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extern struct page *pud_page(pud_t pud);
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@ -951,7 +951,7 @@ static inline int pgd_none(pgd_t pgd)
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static inline int pgd_present(pgd_t pgd)
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{
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return (pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
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return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
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}
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static inline pte_t pgd_pte(pgd_t pgd)
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@ -1258,21 +1258,13 @@ extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
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#define pmd_move_must_withdraw pmd_move_must_withdraw
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struct spinlock;
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static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
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struct spinlock *old_pmd_ptl,
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struct vm_area_struct *vma)
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{
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if (radix_enabled())
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return false;
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/*
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* Archs like ppc64 use pgtable to store per pmd
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* specific information. So when we switch the pmd,
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* we should also withdraw and deposit the pgtable
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*/
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return true;
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}
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extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
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struct spinlock *old_pmd_ptl,
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struct vm_area_struct *vma);
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/*
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* Hash translation mode use the deposited table to store hash pte
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* slot information.
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*/
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#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
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static inline bool arch_needs_pgtable_deposit(void)
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{
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@ -47,6 +47,7 @@ enum perf_event_powerpc_regs {
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PERF_REG_POWERPC_DAR,
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PERF_REG_POWERPC_DSISR,
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PERF_REG_POWERPC_SIER,
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PERF_REG_POWERPC_MMCRA,
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PERF_REG_POWERPC_MAX,
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};
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#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
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@ -852,11 +852,12 @@ start_here:
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/* set up the PTE pointers for the Abatron bdiGDB.
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*/
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tovirt(r6,r6)
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lis r5, abatron_pteptrs@h
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ori r5, r5, abatron_pteptrs@l
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stw r5, 0xf0(0) /* Must match your Abatron config file */
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tophys(r5,r5)
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lis r6, swapper_pg_dir@h
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ori r6, r6, swapper_pg_dir@l
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stw r6, 0(r5)
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/* Now turn on the MMU for real! */
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@ -755,11 +755,12 @@ SYSCALL_DEFINE0(rt_sigreturn)
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if (restore_tm_sigcontexts(current, &uc->uc_mcontext,
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&uc_transact->uc_mcontext))
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goto badframe;
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}
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} else
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#endif
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/* Fall through, for non-TM restore */
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if (!MSR_TM_ACTIVE(msr)) {
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{
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/*
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* Fall through, for non-TM restore
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*
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* Unset MSR[TS] on the thread regs since MSR from user
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* context does not have MSR active, and recheckpoint was
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* not called since restore_tm_sigcontexts() was not called
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@ -967,13 +967,6 @@ unsigned long prepare_ftrace_return(unsigned long parent, unsigned long ip)
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}
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#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
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#if defined(CONFIG_FTRACE_SYSCALLS) && defined(CONFIG_PPC64)
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unsigned long __init arch_syscall_addr(int nr)
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{
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return sys_call_table[nr*2];
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}
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#endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_PPC64 */
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#ifdef PPC64_ELF_ABI_v1
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char *arch_ftrace_match_adjust(char *str, const char *search)
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{
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@ -400,3 +400,25 @@ void arch_report_meminfo(struct seq_file *m)
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atomic_long_read(&direct_pages_count[MMU_PAGE_1G]) << 20);
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}
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#endif /* CONFIG_PROC_FS */
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/*
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* For hash translation mode, we use the deposited table to store hash slot
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* information and they are stored at PTRS_PER_PMD offset from related pmd
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* location. Hence a pmd move requires deposit and withdraw.
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*
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* For radix translation with split pmd ptl, we store the deposited table in the
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* pmd page. Hence if we have different pmd page we need to withdraw during pmd
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* move.
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*
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* With hash we use deposited table always irrespective of anon or not.
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* With radix we use deposited table only for anonymous mapping.
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*/
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int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
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struct spinlock *old_pmd_ptl,
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struct vm_area_struct *vma)
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{
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if (radix_enabled())
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return (new_pmd_ptl != old_pmd_ptl) && vma_is_anonymous(vma);
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return true;
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}
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@ -70,6 +70,7 @@ static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
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PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar),
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PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr),
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PT_REGS_OFFSET(PERF_REG_POWERPC_SIER, dar),
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PT_REGS_OFFSET(PERF_REG_POWERPC_MMCRA, dsisr),
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};
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u64 perf_reg_value(struct pt_regs *regs, int idx)
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@ -83,6 +84,11 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
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!is_sier_available()))
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return 0;
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if (idx == PERF_REG_POWERPC_MMCRA &&
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(IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||
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IS_ENABLED(CONFIG_PPC32)))
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return 0;
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return regs_get_register(regs, pt_regs_offset[idx]);
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}
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@ -237,12 +237,12 @@ static int ocm_debugfs_show(struct seq_file *m, void *v)
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continue;
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seq_printf(m, "PPC4XX OCM : %d\n", ocm->index);
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seq_printf(m, "PhysAddr : %pa[p]\n", &(ocm->phys));
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seq_printf(m, "PhysAddr : %pa\n", &(ocm->phys));
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seq_printf(m, "MemTotal : %d Bytes\n", ocm->memtotal);
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seq_printf(m, "MemTotal(NC) : %d Bytes\n", ocm->nc.memtotal);
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seq_printf(m, "MemTotal(C) : %d Bytes\n\n", ocm->c.memtotal);
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seq_printf(m, "NC.PhysAddr : %pa[p]\n", &(ocm->nc.phys));
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seq_printf(m, "NC.PhysAddr : %pa\n", &(ocm->nc.phys));
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seq_printf(m, "NC.VirtAddr : 0x%p\n", ocm->nc.virt);
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seq_printf(m, "NC.MemTotal : %d Bytes\n", ocm->nc.memtotal);
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seq_printf(m, "NC.MemFree : %d Bytes\n", ocm->nc.memfree);
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@ -252,7 +252,7 @@ static int ocm_debugfs_show(struct seq_file *m, void *v)
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blk->size, blk->owner);
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}
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seq_printf(m, "\nC.PhysAddr : %pa[p]\n", &(ocm->c.phys));
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seq_printf(m, "\nC.PhysAddr : %pa\n", &(ocm->c.phys));
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seq_printf(m, "C.VirtAddr : 0x%p\n", ocm->c.virt);
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seq_printf(m, "C.MemTotal : %d Bytes\n", ocm->c.memtotal);
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seq_printf(m, "C.MemFree : %d Bytes\n", ocm->c.memfree);
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@ -560,7 +560,7 @@ struct iommu_table_group *pnv_try_setup_npu_table_group(struct pnv_ioda_pe *pe)
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}
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} else {
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/* Create a group for 1 GPU and attached NPUs for POWER8 */
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pe->npucomp = kzalloc(sizeof(pe->npucomp), GFP_KERNEL);
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pe->npucomp = kzalloc(sizeof(*pe->npucomp), GFP_KERNEL);
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table_group = &pe->npucomp->table_group;
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table_group->ops = &pnv_npu_peers_ops;
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iommu_register_group(table_group, hose->global_number,
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@ -2681,7 +2681,8 @@ static void pnv_pci_ioda_setup_iommu_api(void)
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list_for_each_entry(hose, &hose_list, list_node) {
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phb = hose->private_data;
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if (phb->type == PNV_PHB_NPU_NVLINK)
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if (phb->type == PNV_PHB_NPU_NVLINK ||
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phb->type == PNV_PHB_NPU_OCAPI)
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continue;
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list_for_each_entry(pe, &phb->ioda.pe_list, list) {
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@ -43,6 +43,7 @@ static int drc_pmem_bind(struct papr_scm_priv *p)
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{
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unsigned long ret[PLPAR_HCALL_BUFSIZE];
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uint64_t rc, token;
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uint64_t saved = 0;
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/*
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* When the hypervisor cannot map all the requested memory in a single
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@ -56,6 +57,8 @@ static int drc_pmem_bind(struct papr_scm_priv *p)
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rc = plpar_hcall(H_SCM_BIND_MEM, ret, p->drc_index, 0,
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p->blocks, BIND_ANY_ADDR, token);
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token = ret[0];
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if (!saved)
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saved = ret[1];
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cond_resched();
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} while (rc == H_BUSY);
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@ -64,7 +67,7 @@ static int drc_pmem_bind(struct papr_scm_priv *p)
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return -ENXIO;
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}
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p->bound_addr = ret[1];
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p->bound_addr = saved;
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dev_dbg(&p->pdev->dev, "bound drc %x to %pR\n", p->drc_index, &p->res);
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@ -264,7 +264,9 @@ void __init pSeries_final_fixup(void)
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if (!of_device_is_compatible(nvdn->parent,
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"ibm,power9-npu"))
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continue;
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#ifdef CONFIG_PPC_POWERNV
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WARN_ON_ONCE(pnv_npu2_init(hose));
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#endif
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break;
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}
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}
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@ -47,6 +47,7 @@ enum perf_event_powerpc_regs {
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PERF_REG_POWERPC_DAR,
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PERF_REG_POWERPC_DSISR,
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PERF_REG_POWERPC_SIER,
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PERF_REG_POWERPC_MMCRA,
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PERF_REG_POWERPC_MAX,
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};
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#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
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@ -63,7 +63,8 @@ static const char *reg_names[] = {
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[PERF_REG_POWERPC_TRAP] = "trap",
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[PERF_REG_POWERPC_DAR] = "dar",
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[PERF_REG_POWERPC_DSISR] = "dsisr",
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[PERF_REG_POWERPC_SIER] = "sier"
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[PERF_REG_POWERPC_SIER] = "sier",
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[PERF_REG_POWERPC_MMCRA] = "mmcra"
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};
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static inline const char *perf_reg_name(int id)
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@ -53,6 +53,7 @@ const struct sample_reg sample_reg_masks[] = {
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SMPL_REG(dar, PERF_REG_POWERPC_DAR),
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SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),
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SMPL_REG(sier, PERF_REG_POWERPC_SIER),
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SMPL_REG(mmcra, PERF_REG_POWERPC_MMCRA),
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SMPL_REG_END
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};
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