forked from luck/tmp_suning_uos_patched
mailbox: imx: restructure code to make easy for new MU
Add imx_mu_generic_tx for data send and imx_mu_generic_rx for interrupt data receive. Pack original mu chans related code into imx_mu_init_generic Add tx/rx/init hooks into imx_mu_dcfg With these, it will be a bit easy to introduce i.MX8/8X SCU type MU dedicated to communicate with SCU. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Peng Fan
Jassi Brar
parent
eabb8b8cfe
commit
63b383575c
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@ -36,13 +36,6 @@ enum imx_mu_chan_type {
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IMX_MU_TYPE_RXDB, /* Rx doorbell */
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};
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struct imx_mu_dcfg {
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u32 xTR[4]; /* Transmit Registers */
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u32 xRR[4]; /* Receive Registers */
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u32 xSR; /* Status Register */
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u32 xCR; /* Control Register */
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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@ -67,18 +60,14 @@ struct imx_mu_priv {
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bool side_b;
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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.xTR = {0x0, 0x4, 0x8, 0xc},
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.xRR = {0x10, 0x14, 0x18, 0x1c},
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.xSR = 0x20,
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.xCR = 0x24,
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.xTR = {0x20, 0x24, 0x28, 0x2c},
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.xRR = {0x40, 0x44, 0x48, 0x4c},
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.xSR = 0x60,
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.xCR = 0x64,
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struct imx_mu_dcfg {
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
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int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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void (*init)(struct imx_mu_priv *priv);
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u32 xTR[4]; /* Transmit Registers */
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u32 xRR[4]; /* Receive Registers */
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u32 xSR; /* Status Register */
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u32 xCR; /* Control Register */
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};
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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@ -111,6 +100,40 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
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return val;
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}
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static int imx_mu_generic_tx(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp,
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void *data)
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{
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u32 *arg = data;
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
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break;
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case IMX_MU_TYPE_TXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_generic_rx(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp)
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{
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u32 dat;
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dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
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mbox_chan_received_data(cp->chan, (void *)&dat);
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return 0;
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}
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static void imx_mu_txdb_tasklet(unsigned long data)
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{
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struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
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@ -123,7 +146,7 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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struct mbox_chan *chan = p;
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
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struct imx_mu_con_priv *cp = chan->con_priv;
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u32 val, ctrl, dat;
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u32 val, ctrl;
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ctrl = imx_mu_read(priv, priv->dcfg->xCR);
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val = imx_mu_read(priv, priv->dcfg->xSR);
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@ -152,8 +175,7 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
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mbox_chan_txdone(chan, 0);
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} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
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dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
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mbox_chan_received_data(chan, (void *)&dat);
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priv->dcfg->rx(priv, cp);
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} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
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mbox_chan_received_data(chan, NULL);
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@ -169,23 +191,8 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data)
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{
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
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struct imx_mu_con_priv *cp = chan->con_priv;
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u32 *arg = data;
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
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break;
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case IMX_MU_TYPE_TXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
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return -EINVAL;
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}
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return 0;
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return priv->dcfg->tx(priv, cp, data);
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}
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static int imx_mu_startup(struct mbox_chan *chan)
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@ -280,6 +287,22 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
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static void imx_mu_init_generic(struct imx_mu_priv *priv)
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{
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unsigned int i;
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for (i = 0; i < IMX_MU_CHANS; i++) {
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struct imx_mu_con_priv *cp = &priv->con_priv[i];
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cp->idx = i % 4;
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cp->type = i >> 2;
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cp->chan = &priv->mbox_chans[i];
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priv->mbox_chans[i].con_priv = cp;
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snprintf(cp->irq_desc, sizeof(cp->irq_desc),
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"imx_mu_chan[%i-%i]", cp->type, cp->idx);
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}
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priv->mbox.num_chans = IMX_MU_CHANS;
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priv->mbox.of_xlate = imx_mu_xlate;
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if (priv->side_b)
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return;
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@ -293,7 +316,6 @@ static int imx_mu_probe(struct platform_device *pdev)
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struct device_node *np = dev->of_node;
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struct imx_mu_priv *priv;
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const struct imx_mu_dcfg *dcfg;
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unsigned int i;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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@ -329,32 +351,19 @@ static int imx_mu_probe(struct platform_device *pdev)
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return ret;
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}
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for (i = 0; i < IMX_MU_CHANS; i++) {
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struct imx_mu_con_priv *cp = &priv->con_priv[i];
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cp->idx = i % 4;
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cp->type = i >> 2;
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cp->chan = &priv->mbox_chans[i];
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priv->mbox_chans[i].con_priv = cp;
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snprintf(cp->irq_desc, sizeof(cp->irq_desc),
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"imx_mu_chan[%i-%i]", cp->type, cp->idx);
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}
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priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
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priv->dcfg->init(priv);
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spin_lock_init(&priv->xcr_lock);
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priv->mbox.dev = dev;
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priv->mbox.ops = &imx_mu_ops;
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priv->mbox.chans = priv->mbox_chans;
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priv->mbox.num_chans = IMX_MU_CHANS;
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priv->mbox.of_xlate = imx_mu_xlate;
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priv->mbox.txdone_irq = true;
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platform_set_drvdata(pdev, priv);
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imx_mu_init_generic(priv);
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return devm_mbox_controller_register(dev, &priv->mbox);
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}
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@ -367,6 +376,26 @@ static int imx_mu_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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.tx = imx_mu_generic_tx,
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.rx = imx_mu_generic_rx,
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.init = imx_mu_init_generic,
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.xTR = {0x0, 0x4, 0x8, 0xc},
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.xRR = {0x10, 0x14, 0x18, 0x1c},
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.xSR = 0x20,
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.xCR = 0x24,
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.tx = imx_mu_generic_tx,
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.rx = imx_mu_generic_rx,
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.init = imx_mu_init_generic,
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.xTR = {0x20, 0x24, 0x28, 0x2c},
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.xRR = {0x40, 0x44, 0x48, 0x4c},
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.xSR = 0x60,
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.xCR = 0x64,
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};
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static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
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{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
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