forked from luck/tmp_suning_uos_patched
ASoC: tlv320aic32x4: Use snd_soc_update_bits() in aic32x4_hw_params()
Make the code easier to read by using snd_soc_update_bits() over read/modify/write sequences. Also use separate per-register variables instead of re-using "data". This can prevent accidental over-writing and makes it clear for which register each bit value is intended. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andrew F. Davis
Mark Brown
parent
b7ddd9cab7
commit
64aab89974
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@ -676,7 +676,8 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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{
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struct snd_soc_codec *codec = dai->codec;
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struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
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u8 data;
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u8 iface1_reg = 0;
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u8 dacsetup_reg = 0;
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int i;
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i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
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@ -685,87 +686,88 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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return i;
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}
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/* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
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snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_PLL);
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snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
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/* MCLK as PLL_CLKIN */
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snd_soc_update_bits(codec, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
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AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
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/* PLL as CODEC_CLKIN */
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snd_soc_update_bits(codec, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
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AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
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/* DAC_MOD_CLK as BDIV_CLKIN */
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snd_soc_update_bits(codec, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
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AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
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/* We will fix R value to 1 and will make P & J=K.D as varialble */
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data = snd_soc_read(codec, AIC32X4_PLLPR);
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data &= ~(7 << 4);
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snd_soc_write(codec, AIC32X4_PLLPR,
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(data | (aic32x4_divs[i].p_val << 4) | 0x01));
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/* We will fix R value to 1 and will make P & J=K.D as variable */
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snd_soc_update_bits(codec, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
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/* PLL P value */
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snd_soc_update_bits(codec, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
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aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
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/* PLL J value */
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snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
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/* PLL D value */
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snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
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snd_soc_write(codec, AIC32X4_PLLDLSB,
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(aic32x4_divs[i].pll_d & 0xff));
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snd_soc_write(codec, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
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/* NDAC divider value */
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data = snd_soc_read(codec, AIC32X4_NDAC);
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data &= ~(0x7f);
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snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
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snd_soc_update_bits(codec, AIC32X4_NDAC,
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AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
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/* MDAC divider value */
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data = snd_soc_read(codec, AIC32X4_MDAC);
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data &= ~(0x7f);
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snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
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snd_soc_update_bits(codec, AIC32X4_MDAC,
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AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
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/* DOSR MSB & LSB values */
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snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
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snd_soc_write(codec, AIC32X4_DOSRLSB,
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(aic32x4_divs[i].dosr & 0xff));
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snd_soc_write(codec, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
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/* NADC divider value */
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data = snd_soc_read(codec, AIC32X4_NADC);
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data &= ~(0x7f);
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snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
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snd_soc_update_bits(codec, AIC32X4_NADC,
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AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
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/* MADC divider value */
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data = snd_soc_read(codec, AIC32X4_MADC);
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data &= ~(0x7f);
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snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
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snd_soc_update_bits(codec, AIC32X4_MADC,
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AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
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/* AOSR value */
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snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
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/* BCLK N divider */
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data = snd_soc_read(codec, AIC32X4_BCLKN);
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data &= ~(0x7f);
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snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
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snd_soc_update_bits(codec, AIC32X4_BCLKN,
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AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
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data = snd_soc_read(codec, AIC32X4_IFACE1);
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data = data & ~(3 << 4);
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switch (params_width(params)) {
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case 16:
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data |= (AIC32X4_WORD_LEN_16BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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case 20:
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data |= (AIC32X4_WORD_LEN_20BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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case 24:
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data |= (AIC32X4_WORD_LEN_24BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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case 32:
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data |= (AIC32X4_WORD_LEN_32BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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}
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snd_soc_write(codec, AIC32X4_IFACE1, data);
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snd_soc_update_bits(codec, AIC32X4_IFACE1,
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AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
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if (params_channels(params) == 1) {
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data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
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dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
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} else {
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if (aic32x4->swapdacs)
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data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
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dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
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else
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data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
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dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
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}
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snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
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data);
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snd_soc_update_bits(codec, AIC32X4_DACSETUP,
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AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
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return 0;
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}
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@ -115,21 +115,29 @@ int aic32x4_remove(struct device *dev);
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/* AIC32X4_PLLPR */
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#define AIC32X4_PLLEN BIT(7)
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#define AIC32X4_PLL_P_MASK GENMASK(6, 4)
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#define AIC32X4_PLL_P_SHIFT (4)
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#define AIC32X4_PLL_R_MASK GENMASK(3, 0)
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/* AIC32X4_NDAC */
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#define AIC32X4_NDACEN BIT(7)
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#define AIC32X4_NDAC_MASK GENMASK(6, 0)
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/* AIC32X4_MDAC */
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#define AIC32X4_MDACEN BIT(7)
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#define AIC32X4_MDAC_MASK GENMASK(6, 0)
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/* AIC32X4_NADC */
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#define AIC32X4_NADCEN BIT(7)
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#define AIC32X4_NADC_MASK GENMASK(6, 0)
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/* AIC32X4_MADC */
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#define AIC32X4_MADCEN BIT(7)
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#define AIC32X4_MADC_MASK GENMASK(6, 0)
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/* AIC32X4_BCLKN */
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#define AIC32X4_BCLKEN BIT(7)
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#define AIC32X4_BCLK_MASK GENMASK(6, 0)
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/* AIC32X4_IFACE1 */
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#define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6)
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