forked from luck/tmp_suning_uos_patched
System-specific handling of bus errors for DECstation variations
supporting parity errors only for memory (Pmax/3min/Maxine). Fixes for resources decoded by the KN04/KN05 MB ASIC. Additional clean-ups for the ECC handler. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
Ralf Baechle
parent
3b2396d972
commit
64dac503e8
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@ -2,8 +2,8 @@
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# Makefile for the DECstation family specific parts of the kernel
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#
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obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \
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setup.o time.o
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obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
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kn02-irq.o kn02xa-berr.o reset.o setup.o time.o
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obj-$(CONFIG_PROM_CONSOLE) += promcon.o
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obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
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@ -6,7 +6,7 @@
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* 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
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* 5900/260 (KN05) systems.
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*
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* Copyright (c) 2003 Maciej W. Rozycki
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* Copyright (c) 2003, 2005 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -15,6 +15,7 @@
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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@ -57,7 +58,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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const char *kind, *agent, *cycle, *event;
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const char *status = "", *xbit = "", *fmt = "";
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dma_addr_t address;
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unsigned long address;
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u16 syn = 0, sngl;
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int i = 0;
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@ -66,7 +67,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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u32 chksyn = *kn0x_chksyn;
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int action = MIPS_BE_FATAL;
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/* For non-ECC ack ASAP, so any subsequent errors get caught. */
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/* For non-ECC ack ASAP, so that any subsequent errors get caught. */
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if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
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dec_ecc_be_ack();
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@ -74,7 +75,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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if (!(erraddr & KN0X_EAR_VALID)) {
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/* No idea what happened. */
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printk(KERN_ALERT "Unidentified bus error %s.\n", kind);
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printk(KERN_ALERT "Unidentified bus error %s\n", kind);
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return action;
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}
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@ -126,7 +127,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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/* Ack now, no rewrite will happen. */
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dec_ecc_be_ack();
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fmt = KERN_ALERT "%s" "invalid.\n";
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fmt = KERN_ALERT "%s" "invalid\n";
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} else {
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sngl = syn & KN0X_ESR_SNGLO;
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syn &= KN0X_ESR_SYNLO;
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@ -161,12 +162,12 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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if (syn == 0x01) {
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error "
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"at check bit C%s.\n";
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"at check bit C%s\n";
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xbit = "X";
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} else {
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error "
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"at check bit C%s%u.\n";
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"at check bit C%s%u\n";
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}
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i = syn >> 2;
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} else {
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@ -176,16 +177,16 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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if (i < 32)
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error "
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"at data bit D%s%u.\n";
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"at data bit D%s%u\n";
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else
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error.\n";
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"%#04x -- %s bit error\n";
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}
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}
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}
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if (action != MIPS_BE_FIXUP)
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printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n",
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printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
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kind, agent, cycle, event, address);
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if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
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@ -207,8 +208,8 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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return IRQ_HANDLED;
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/*
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* FIXME: Find affected processes and kill them, otherwise we
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* must die.
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* FIXME: Find the affected processes and kill them, otherwise
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* we must die.
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*
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* The interrupt is asynchronously delivered thus EPC and RA
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* may be irrelevant, but are printed for a reference.
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@ -235,7 +236,7 @@ static inline void dec_kn02_be_init(void)
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spin_lock_irqsave(&kn02_lock, flags);
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/* Preset write-only bits of the Control Register cache. */
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cached_kn02_csr = *csr | KN03_CSR_LEDS;
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cached_kn02_csr = *csr | KN02_CSR_LEDS;
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/* Set normal ECC detection and generation. */
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cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
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@ -250,7 +251,7 @@ static inline void dec_kn02_be_init(void)
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static inline void dec_kn03_be_init(void)
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{
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volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR);
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volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR);
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volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR);
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kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
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kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
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@ -265,7 +266,7 @@ static inline void dec_kn03_be_init(void)
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*mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
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KN03_MCR_CORRECT;
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if (current_cpu_data.cputype == CPU_R4400SC)
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*mbcs |= KN05_MB_CSR_EE;
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*mbcs |= KN4K_MB_CSR_EE;
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fast_iob();
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}
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@ -4,7 +4,7 @@
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* DECstation 5000/200 (KN02) Control and Status Register
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* interrupts.
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*
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* Copyright (c) 2002, 2003 Maciej W. Rozycki
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* Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -111,7 +111,7 @@ void __init init_kn02_irqs(int base)
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/* Mask interrupts. */
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spin_lock_irqsave(&kn02_lock, flags);
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cached_kn02_csr &= ~KN03_CSR_IOINTEN;
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cached_kn02_csr &= ~KN02_CSR_IOINTEN;
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*csr = cached_kn02_csr;
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iob();
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spin_unlock_irqrestore(&kn02_lock, flags);
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@ -113,7 +113,16 @@ void __init dec_be_init(void)
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{
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switch (mips_machtype) {
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case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
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board_be_handler = dec_kn01_be_handler;
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busirq.handler = dec_kn01_be_interrupt;
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busirq.flags |= SA_SHIRQ;
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dec_kn01_be_init();
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break;
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case MACH_DS5000_1XX: /* DS5000/1xx 3min */
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case MACH_DS5000_XX: /* DS5000/xx Maxine */
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board_be_handler = dec_kn02xa_be_handler;
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busirq.handler = dec_kn02xa_be_interrupt;
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dec_kn02xa_be_init();
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break;
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case MACH_DS5000_200: /* DS5000/200 3max */
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case MACH_DS5000_2X0: /* DS5000/240 3max+ */
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@ -49,7 +49,8 @@ struct pt_regs;
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extern void dec_ecc_be_init(void);
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extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
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extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs);
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extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id,
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struct pt_regs *regs);
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#endif
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#endif /* __ASM_MIPS_DEC_ECC_H */
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@ -8,7 +8,7 @@
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*
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* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
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* are by courtesy of Chris Fraser.
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* Copyright (C) 2002, 2003 Maciej W. Rozycki
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* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
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*/
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#ifndef __ASM_MIPS_DEC_KN01_H
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#define __ASM_MIPS_DEC_KN01_H
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@ -80,4 +80,22 @@
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#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
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#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
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#ifndef __ASSEMBLY__
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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struct pt_regs;
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extern u16 cached_kn01_csr;
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extern spinlock_t kn01_lock;
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extern void dec_kn01_be_init(void);
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extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
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extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
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struct pt_regs *regs);
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#endif
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#endif /* __ASM_MIPS_DEC_KN01_H */
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@ -8,16 +8,11 @@
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*
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* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
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* are by courtesy of Chris Fraser.
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* Copyright (C) 2002, 2003 Maciej W. Rozycki
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* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
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*/
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#ifndef __ASM_MIPS_DEC_KN02_H
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#define __ASM_MIPS_DEC_KN02_H
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#endif
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#include <asm/addrspace.h>
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#include <asm/dec/ecc.h>
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@ -53,8 +48,8 @@
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#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
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#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
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#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
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#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
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#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
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#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
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#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
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#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
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#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
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#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
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@ -63,8 +58,8 @@
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#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
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#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
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#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
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#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
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#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
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#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
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#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
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/*
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@ -98,6 +93,10 @@
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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#include <linux/types.h>
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extern u32 cached_kn02_csr;
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extern spinlock_t kn02_lock;
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extern void init_kn02_irqs(int base);
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@ -9,7 +9,7 @@
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*
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* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
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* are by courtesy of Chris Fraser.
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* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
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* Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
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*
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* These are addresses which have to be known early in the boot process.
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* For other addresses refer to tc.h, ioasic_addrs.h and friends.
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@ -52,8 +52,13 @@
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#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
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#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
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#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
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#define KN02XA_MER_RES_12 (0x3<<12) /* unused */
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#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */
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#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */
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#define KN02XA_MER_RES_12 (1<<12) /* unused */
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#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
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#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */
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#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */
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#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */
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#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */
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#define KN02XA_MER_RES_0 (0xff<<0) /* unused */
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/*
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@ -72,4 +77,17 @@
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#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
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#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
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#ifndef __ASSEMBLY__
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#include <linux/interrupt.h>
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struct pt_regs;
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extern void dec_kn02xa_be_init(void);
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extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
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extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
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struct pt_regs *regs);
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#endif
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#endif /* __ASM_MIPS_DEC_KN02XA_H */
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@ -1,10 +1,12 @@
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/*
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* include/asm-mips/dec/kn05.h
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*
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* DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
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* DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
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* or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
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* KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
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* definitions.
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*
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* Copyright (C) 2002, 2003 Maciej W. Rozycki
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* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
|
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
|
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|
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@ -13,59 +15,62 @@
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*
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* WARNING! All this information is pure guesswork based on the
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* ROM. It is provided here in hope it will give someone some
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* food for thought. No documentation for the KN05 module has
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* been located so far.
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* food for thought. No documentation for the KN05 nor the KN04
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* module has been located so far.
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*/
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#ifndef __ASM_MIPS_DEC_KN05_H
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#define __ASM_MIPS_DEC_KN05_H
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#include <asm/addrspace.h>
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#include <asm/dec/ioasic_addrs.h>
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/*
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* The oncard MB (Memory Buffer) ASIC provides an additional address
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* decoder. Certain address ranges within the "high" 16 slots are
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* passed to the I/O ASIC's decoder like with the KN03. Others are
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* handled locally. "Low" slots are always passed.
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* passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
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* Others are handled locally. "Low" slots are always passed.
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*/
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#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */
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#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */
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#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
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#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
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#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */
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#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */
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#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */
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#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */
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#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */
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#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */
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#define KN4K_SLOT_BASE KSEG1ADDR(0x1fc00000)
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#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
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#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
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#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
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#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
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#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
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#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
|
||||
#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
|
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#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
|
||||
#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
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||||
#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
|
||||
#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
|
||||
#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
|
||||
#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
|
||||
#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
|
||||
#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
|
||||
#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
|
||||
|
||||
/*
|
||||
* Bits for the MB interrupt register.
|
||||
* The register appears read-only.
|
||||
*/
|
||||
#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */
|
||||
#define KN05_MB_INT_RTC (1<<1) /* RTC? */
|
||||
#define KN05_MB_INT_MT (1<<3) /* ??? */
|
||||
#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
|
||||
#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
|
||||
#define KN4K_MB_INT_MT (1<<3) /* ??? */
|
||||
|
||||
/*
|
||||
* Bits for the MB control & status register.
|
||||
* Set to 0x00bf8001 on my system by the ROM.
|
||||
*/
|
||||
#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */
|
||||
#define KN05_MB_CSR_F (1<<1) /* ??? */
|
||||
#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */
|
||||
#define KN05_MB_CSR_OD (1<<10) /* ??? */
|
||||
#define KN05_MB_CSR_CP (1<<11) /* ??? */
|
||||
#define KN05_MB_CSR_UNC (1<<12) /* ??? */
|
||||
#define KN05_MB_CSR_IM (1<<13) /* ??? */
|
||||
#define KN05_MB_CSR_NC (1<<14) /* ??? */
|
||||
#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
|
||||
#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */
|
||||
#define KN05_MB_CSR_FW (1<<21) /* ??? */
|
||||
#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
|
||||
#define KN4K_MB_CSR_F (1<<1) /* ??? */
|
||||
#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
|
||||
#define KN4K_MB_CSR_OD (1<<10) /* ??? */
|
||||
#define KN4K_MB_CSR_CP (1<<11) /* ??? */
|
||||
#define KN4K_MB_CSR_UNC (1<<12) /* ??? */
|
||||
#define KN4K_MB_CSR_IM (1<<13) /* ??? */
|
||||
#define KN4K_MB_CSR_NC (1<<14) /* ??? */
|
||||
#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
|
||||
#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */
|
||||
#define KN4K_MB_CSR_FW (1<<21) /* ??? */
|
||||
|
||||
#endif /* __ASM_MIPS_DEC_KN05_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user