forked from luck/tmp_suning_uos_patched
bnx2x: handle CHIP_REVISION during init_one
The macro `CHIP_IS_E1x' requires `bp' to be initialized. As `bp' is not yet initialized during this phase of `bnx2x_init_dev', it accessed uninitialized fields in the struct. Signed-off-by: Ariel Elior <ariele@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1fdf155158
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@ -10536,6 +10536,9 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
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{
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{
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struct bnx2x *bp;
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struct bnx2x *bp;
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int rc;
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int rc;
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bool chip_is_e1x = (board_type == BCM57710 ||
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board_type == BCM57711 ||
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board_type == BCM57711E);
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SET_NETDEV_DEV(dev, &pdev->dev);
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SET_NETDEV_DEV(dev, &pdev->dev);
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bp = netdev_priv(dev);
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bp = netdev_priv(dev);
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@ -10624,7 +10627,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
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REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
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if (CHIP_IS_E1x(bp)) {
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if (chip_is_e1x) {
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REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
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REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
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@ -10635,9 +10638,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
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* Enable internal target-read (in case we are probed after PF FLR).
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* Enable internal target-read (in case we are probed after PF FLR).
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* Must be done prior to any BAR read access. Only for 57712 and up
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* Must be done prior to any BAR read access. Only for 57712 and up
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*/
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*/
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if (board_type != BCM57710 &&
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if (!chip_is_e1x)
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board_type != BCM57711 &&
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board_type != BCM57711E)
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REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
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REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
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/* Reset the load counter */
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/* Reset the load counter */
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