forked from luck/tmp_suning_uos_patched
dt-bindings: gpio: Convert snps,dw-apb-gpio to DT schema
Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces Synopsys DW GPIO legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with generic DW I2C controller indicated by the "snps,dw-apb-gpio" compatible string and to provide a mandatory registers memory range. It may also have an optional clock and reset phandle references. There must be specified at least one subnode with "snps,dw-apb-gpio-port" compatible string indicating the GPIO port, which would actually export the GPIO controller functionality. Such nodes should have traditional GPIO controller properties together with optional interrupt-controller attributes if the corresponding controller was synthesized to detect and report the input values change to the parental IRQ controller. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200323195401.30338-2-Sergey.Semin@baikalelectronics.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Serge Semin
Linus Walleij
parent
04fd1ca779
commit
657a06df99
129
Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
Normal file
129
Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare APB GPIO controller
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description: |
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Synopsys DesignWare GPIO controllers have a configurable number of ports,
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each of which are intended to be represented as child nodes with the generic
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GPIO-controller properties as desribed in this bindings file.
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maintainers:
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- Hoan Tran <hoan@os.amperecomputing.com>
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properties:
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$nodename:
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pattern: "^gpio@[0-9a-f]+$"
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compatible:
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const: snps,dw-apb-gpio
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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maxItems: 1
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clocks:
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items:
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- description: APB interface clock source
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clock-names:
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items:
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- const: bus
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resets:
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maxItems: 1
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patternProperties:
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"^gpio-(port|controller)@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: snps,dw-apb-gpio-port
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reg:
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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const: 2
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snps,nr-gpios:
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description: The number of GPIO pins exported by the port.
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default: 32
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 1
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maximum: 32
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interrupts:
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description: |
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The interrupts to the parent controller raised when GPIOs generate
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the interrupts. If the controller provides one combined interrupt
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for all GPIOs, specify a single interrupt. If the controller provides
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one interrupt for each GPIO, provide a list of interrupts that
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correspond to each of the GPIO pins.
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minItems: 1
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maxItems: 32
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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dependencies:
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interrupt-controller: [ interrupts ]
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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gpio: gpio@20000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&vic1>;
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interrupts = <0>;
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};
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portb: gpio-port@1 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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};
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};
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...
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@ -1,65 +0,0 @@
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* Synopsys DesignWare APB GPIO controller
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Required properties:
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- compatible : Should contain "snps,dw-apb-gpio"
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- reg : Address and length of the register set for the device.
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- #address-cells : should be 1 (for addressing port subnodes).
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- #size-cells : should be 0 (port subnodes).
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The GPIO controller has a configurable number of ports, each of which are
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represented as child nodes with the following properties:
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Required properties:
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- compatible : "snps,dw-apb-gpio-port"
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- gpio-controller : Marks the device node as a gpio controller.
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- #gpio-cells : Should be two. The first cell is the pin number and
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the second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- reg : The integer port index of the port, a single cell.
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Optional properties:
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- interrupt-controller : The first port may be configured to be an interrupt
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controller.
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt. Shall be set to 2. The first cell defines the interrupt number,
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the second encodes the triger flags encoded as described in
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Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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- interrupts : The interrupts to the parent controller raised when GPIOs
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generate the interrupts. If the controller provides one combined interrupt
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for all GPIOs, specify a single interrupt. If the controller provides one
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interrupt for each GPIO, provide a list of interrupts that correspond to each
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of the GPIO pins. When specifying multiple interrupts, if any are unconnected,
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use the interrupts-extended property to specify the interrupts and set the
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interrupt controller handle for unused interrupts to 0.
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- snps,nr-gpios : The number of pins in the port, a single cell.
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- resets : Reset line for the controller.
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Example:
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gpio: gpio@20000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&vic1>;
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interrupts = <0>;
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};
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portb: gpio@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <1>;
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};
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};
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