AcoSail/kernel_optimize_test
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Merge branch 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac

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Pull EDAC updates from Mauro Carvalho Chehab.

* 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac:
  sb_edac: add support for Haswell based systems
  sb_edac: Fix mix tab/spaces alignments
  edac: add DDR4 and RDDR4
  sb_edac: remove bogus assumption on mc ordering
  sb_edac: make minimal use of channel_mask
  sb_edac: fix socket detection on Ivy Bridge controllers
  sb_edac: update Kconfig description
  sb_edac: search devices using product id
  sb_edac: make RIR limit retrieval per model
  sb_edac: make node id retrieval per model
  sb_edac: make memory type detection per memory controller
This commit is contained in:
Linus Torvalds 2014-08-15 17:56:45 -06:00
commit 68ffeca4f4
4 changed files with 552 additions and 273 deletions
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4
drivers/edac/Kconfig
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@ -253,12 +253,12 @@ config EDAC_I7300
Clarksboro MCH (Intel 7300 chipset).
config EDAC_SBRIDGE
tristate "Intel Sandy-Bridge Integrated MC"
tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
depends on PCI_MMCONFIG
help
Support for error detection and correction the Intel
Sandy Bridge Integrated Memory Controller.
Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
config EDAC_MPC85XX
tristate "Freescale MPC83xx / MPC85xx"

4
drivers/edac/edac_mc_sysfs.c
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@ -108,7 +108,9 @@ static const char * const mem_types[] = {
[MEM_RDDR2] = "Registered-DDR2",
[MEM_XDR] = "XDR",
[MEM_DDR3] = "Unbuffered-DDR3",
[MEM_RDDR3] = "Registered-DDR3"
[MEM_RDDR3] = "Registered-DDR3",
[MEM_DDR4] = "Unbuffered-DDR4",
[MEM_RDDR4] = "Registered-DDR4"
};
static const char * const dev_types[] = {

812
drivers/edac/sb_edac.c
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File diff suppressed because it is too large Load Diff

5
include/linux/edac.h
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@ -194,6 +194,9 @@ static inline char *mc_event_error_type(const unsigned int err_type)
* @MEM_DDR3: DDR3 RAM
* @MEM_RDDR3: Registered DDR3 RAM
* This is a variant of the DDR3 memories.
* @MEM_DDR4: DDR4 RAM
* @MEM_RDDR4: Registered DDR4 RAM
* This is a variant of the DDR4 memories.
*/
enum mem_type {
MEM_EMPTY = 0,
@ -213,6 +216,8 @@ enum mem_type {
MEM_XDR,
MEM_DDR3,
MEM_RDDR3,
MEM_DDR4,
MEM_RDDR4,
};
#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)