forked from luck/tmp_suning_uos_patched
KVM/ARM fixes for 5.1
- Fix THP handling in the presence of pre-existing PTEs - Honor request for PTE mappings even when THPs are available - GICv4 performance improvement - Take the srcu lock when writing to guest-controlled ITS data structures - Reset the virtual PMU in preemptible context - Various cleanups -----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlycy1MVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDlJkQAK0mjfSOyZpeYX48XqE2Vnmr0HH2 bfwh63jv2apR4frlT9XiSV4xUEhM8n6mblnSSuXZlykR74ZxzrCb0QKROTe67jAQ HxJrK+9JuKZE4VTKtpx+JIyr377NosY/cx2E87Agdof/+L2tqfjKAnI6MLsVIuca H3F6SH2YVhcPcf0+6nKPUF5wacKlsDZfmrq3Hgk1MbgXG5UmFdjBFlcTUOFSumkK E4hD93VHiQUDKvJL/qRN3p940c0lVOcDxK9Gu1AhmosvdLYEZJgtZeLBvysDH6Xl xbq5EU5q/Gks/DEQqallaOiocREc3mZCUlF+pC1sLUHalEClEvr47hlXCLHz9RzA yV0wW7Foo0oZb+zQyswrCZbAhpO7Vuqd00ghSgV6n6hTS2O7t9syiSe3QCvgCkoy YZ+Eogx66m68bvbBqFrLwGHUlg+XSpw8ZZ5sh6d6iCVjSVp7ptbmxMgxuMQoJgVT jl7WbXWYdZ2f3gYlKhtN+3IGxFIAUvFeSxFxJYnwWQPEcR6gY/lBCbwGTL5WT96F K12V6egTau3QrG+hP+DYPwzWNPcC5oNlayOKNPlTuiwzp2PsSdBAMpEN4Kadl8m8 cMvvRhrcpmrTZdLLQATU9O9A75M1si1a9zaLuC1icYZwYeV593BnqvBBRwS9r/1S ccg/6EkNpWZby3yd =mpQX -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master KVM/ARM fixes for 5.1 - Fix THP handling in the presence of pre-existing PTEs - Honor request for PTE mappings even when THPs are available - GICv4 performance improvement - Take the srcu lock when writing to guest-controlled ITS data structures - Reset the virtual PMU in preemptible context - Various cleanups
This commit is contained in:
Paolo Bonzini
commit
690edec54c
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@ -381,6 +381,17 @@ static inline int kvm_read_guest_lock(struct kvm *kvm,
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return ret;
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}
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static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
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const void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_write_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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static inline void *kvm_get_hyp_vector(void)
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{
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switch(read_cpuid_part()) {
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@ -75,6 +75,8 @@ static inline bool kvm_stage2_has_pud(struct kvm *kvm)
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#define S2_PMD_MASK PMD_MASK
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#define S2_PMD_SIZE PMD_SIZE
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#define S2_PUD_MASK PUD_MASK
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#define S2_PUD_SIZE PUD_SIZE
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static inline bool kvm_stage2_has_pmd(struct kvm *kvm)
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{
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@ -445,6 +445,17 @@ static inline int kvm_read_guest_lock(struct kvm *kvm,
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return ret;
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}
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static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
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const void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_write_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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#ifdef CONFIG_KVM_INDIRECT_VECTORS
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/*
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* EL2 vectors can be mapped and rerouted in a number of ways,
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@ -123,6 +123,9 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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int ret = -EINVAL;
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bool loaded;
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/* Reset PMU outside of the non-preemptible section */
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kvm_pmu_vcpu_reset(vcpu);
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preempt_disable();
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loaded = (vcpu->cpu != -1);
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if (loaded)
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@ -170,9 +173,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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vcpu->arch.reset_state.reset = false;
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}
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/* Reset PMU */
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kvm_pmu_vcpu_reset(vcpu);
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/* Default workaround setup is enabled (if supported) */
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if (kvm_arm_have_ssbd() == KVM_SSBD_KERNEL)
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vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
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@ -222,7 +222,7 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
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}
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}
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if (used_lrs) {
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if (used_lrs || cpu_if->its_vpe.its_vm) {
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int i;
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u32 elrsr;
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@ -247,7 +247,7 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
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u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
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int i;
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if (used_lrs) {
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if (used_lrs || cpu_if->its_vpe.its_vm) {
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write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
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for (i = 0; i < used_lrs; i++)
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@ -102,8 +102,7 @@ static bool kvm_is_device_pfn(unsigned long pfn)
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* @addr: IPA
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* @pmd: pmd pointer for IPA
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*
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* Function clears a PMD entry, flushes addr 1st and 2nd stage TLBs. Marks all
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* pages in the range dirty.
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* Function clears a PMD entry, flushes addr 1st and 2nd stage TLBs.
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*/
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static void stage2_dissolve_pmd(struct kvm *kvm, phys_addr_t addr, pmd_t *pmd)
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{
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@ -121,8 +120,7 @@ static void stage2_dissolve_pmd(struct kvm *kvm, phys_addr_t addr, pmd_t *pmd)
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* @addr: IPA
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* @pud: pud pointer for IPA
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*
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* Function clears a PUD entry, flushes addr 1st and 2nd stage TLBs. Marks all
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* pages in the range dirty.
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* Function clears a PUD entry, flushes addr 1st and 2nd stage TLBs.
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*/
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static void stage2_dissolve_pud(struct kvm *kvm, phys_addr_t addr, pud_t *pudp)
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{
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@ -899,9 +897,8 @@ int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
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* kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation.
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* @kvm: The KVM struct pointer for the VM.
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*
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* Allocates only the stage-2 HW PGD level table(s) (can support either full
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* 40-bit input addresses or limited to 32-bit input addresses). Clears the
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* allocated pages.
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* Allocates only the stage-2 HW PGD level table(s) of size defined by
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* stage2_pgd_size(kvm).
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*
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* Note we don't need locking here as this is only called when the VM is
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* created, which can only be done once.
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@ -1067,25 +1064,43 @@ static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache
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{
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pmd_t *pmd, old_pmd;
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retry:
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pmd = stage2_get_pmd(kvm, cache, addr);
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VM_BUG_ON(!pmd);
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old_pmd = *pmd;
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/*
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* Multiple vcpus faulting on the same PMD entry, can
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* lead to them sequentially updating the PMD with the
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* same value. Following the break-before-make
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* (pmd_clear() followed by tlb_flush()) process can
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* hinder forward progress due to refaults generated
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* on missing translations.
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*
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* Skip updating the page table if the entry is
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* unchanged.
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*/
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if (pmd_val(old_pmd) == pmd_val(*new_pmd))
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return 0;
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if (pmd_present(old_pmd)) {
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/*
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* Multiple vcpus faulting on the same PMD entry, can
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* lead to them sequentially updating the PMD with the
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* same value. Following the break-before-make
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* (pmd_clear() followed by tlb_flush()) process can
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* hinder forward progress due to refaults generated
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* on missing translations.
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* If we already have PTE level mapping for this block,
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* we must unmap it to avoid inconsistent TLB state and
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* leaking the table page. We could end up in this situation
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* if the memory slot was marked for dirty logging and was
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* reverted, leaving PTE level mappings for the pages accessed
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* during the period. So, unmap the PTE level mapping for this
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* block and retry, as we could have released the upper level
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* table in the process.
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*
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* Skip updating the page table if the entry is
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* unchanged.
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* Normal THP split/merge follows mmu_notifier callbacks and do
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* get handled accordingly.
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*/
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if (pmd_val(old_pmd) == pmd_val(*new_pmd))
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return 0;
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if (!pmd_thp_or_huge(old_pmd)) {
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unmap_stage2_range(kvm, addr & S2_PMD_MASK, S2_PMD_SIZE);
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goto retry;
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}
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/*
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* Mapping in huge pages should only happen through a
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* fault. If a page is merged into a transparent huge
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@ -1097,8 +1112,7 @@ static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache
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* should become splitting first, unmapped, merged,
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* and mapped back in on-demand.
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*/
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VM_BUG_ON(pmd_pfn(old_pmd) != pmd_pfn(*new_pmd));
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WARN_ON_ONCE(pmd_pfn(old_pmd) != pmd_pfn(*new_pmd));
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pmd_clear(pmd);
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kvm_tlb_flush_vmid_ipa(kvm, addr);
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} else {
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@ -1114,6 +1128,7 @@ static int stage2_set_pud_huge(struct kvm *kvm, struct kvm_mmu_memory_cache *cac
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{
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pud_t *pudp, old_pud;
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retry:
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pudp = stage2_get_pud(kvm, cache, addr);
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VM_BUG_ON(!pudp);
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@ -1121,14 +1136,23 @@ static int stage2_set_pud_huge(struct kvm *kvm, struct kvm_mmu_memory_cache *cac
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/*
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* A large number of vcpus faulting on the same stage 2 entry,
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* can lead to a refault due to the
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* stage2_pud_clear()/tlb_flush(). Skip updating the page
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* tables if there is no change.
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* can lead to a refault due to the stage2_pud_clear()/tlb_flush().
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* Skip updating the page tables if there is no change.
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*/
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if (pud_val(old_pud) == pud_val(*new_pudp))
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return 0;
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if (stage2_pud_present(kvm, old_pud)) {
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/*
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* If we already have table level mapping for this block, unmap
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* the range for this block and retry.
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*/
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if (!stage2_pud_huge(kvm, old_pud)) {
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unmap_stage2_range(kvm, addr & S2_PUD_MASK, S2_PUD_SIZE);
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goto retry;
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}
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WARN_ON_ONCE(kvm_pud_pfn(old_pud) != kvm_pud_pfn(*new_pudp));
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stage2_pud_clear(kvm, pudp);
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kvm_tlb_flush_vmid_ipa(kvm, addr);
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} else {
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@ -1451,13 +1475,11 @@ static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud,
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}
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/**
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* stage2_wp_puds - write protect PGD range
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* @pgd: pointer to pgd entry
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* @addr: range start address
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* @end: range end address
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*
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* Process PUD entries, for a huge PUD we cause a panic.
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*/
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* stage2_wp_puds - write protect PGD range
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* @pgd: pointer to pgd entry
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* @addr: range start address
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* @end: range end address
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*/
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static void stage2_wp_puds(struct kvm *kvm, pgd_t *pgd,
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phys_addr_t addr, phys_addr_t end)
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{
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@ -1594,8 +1616,9 @@ static void kvm_send_hwpoison_signal(unsigned long address,
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send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, lsb, current);
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}
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static bool fault_supports_stage2_pmd_mappings(struct kvm_memory_slot *memslot,
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unsigned long hva)
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static bool fault_supports_stage2_huge_mapping(struct kvm_memory_slot *memslot,
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unsigned long hva,
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unsigned long map_size)
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{
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gpa_t gpa_start;
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hva_t uaddr_start, uaddr_end;
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@ -1610,34 +1633,34 @@ static bool fault_supports_stage2_pmd_mappings(struct kvm_memory_slot *memslot,
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/*
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* Pages belonging to memslots that don't have the same alignment
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* within a PMD for userspace and IPA cannot be mapped with stage-2
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* PMD entries, because we'll end up mapping the wrong pages.
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* within a PMD/PUD for userspace and IPA cannot be mapped with stage-2
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* PMD/PUD entries, because we'll end up mapping the wrong pages.
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*
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* Consider a layout like the following:
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*
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* memslot->userspace_addr:
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* +-----+--------------------+--------------------+---+
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* |abcde|fgh Stage-1 PMD | Stage-1 PMD tv|xyz|
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* |abcde|fgh Stage-1 block | Stage-1 block tv|xyz|
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* +-----+--------------------+--------------------+---+
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*
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* memslot->base_gfn << PAGE_SIZE:
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* +---+--------------------+--------------------+-----+
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* |abc|def Stage-2 PMD | Stage-2 PMD |tvxyz|
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* |abc|def Stage-2 block | Stage-2 block |tvxyz|
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* +---+--------------------+--------------------+-----+
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*
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* If we create those stage-2 PMDs, we'll end up with this incorrect
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* If we create those stage-2 blocks, we'll end up with this incorrect
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* mapping:
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* d -> f
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* e -> g
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* f -> h
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*/
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if ((gpa_start & ~S2_PMD_MASK) != (uaddr_start & ~S2_PMD_MASK))
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if ((gpa_start & (map_size - 1)) != (uaddr_start & (map_size - 1)))
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return false;
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/*
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* Next, let's make sure we're not trying to map anything not covered
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* by the memslot. This means we have to prohibit PMD size mappings
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* for the beginning and end of a non-PMD aligned and non-PMD sized
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* by the memslot. This means we have to prohibit block size mappings
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* for the beginning and end of a non-block aligned and non-block sized
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* memory slot (illustrated by the head and tail parts of the
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* userspace view above containing pages 'abcde' and 'xyz',
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* respectively).
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@ -1646,8 +1669,8 @@ static bool fault_supports_stage2_pmd_mappings(struct kvm_memory_slot *memslot,
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* userspace_addr or the base_gfn, as both are equally aligned (per
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* the check above) and equally sized.
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*/
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return (hva & S2_PMD_MASK) >= uaddr_start &&
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(hva & S2_PMD_MASK) + S2_PMD_SIZE <= uaddr_end;
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return (hva & ~(map_size - 1)) >= uaddr_start &&
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(hva & ~(map_size - 1)) + map_size <= uaddr_end;
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}
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static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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@ -1676,12 +1699,6 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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return -EFAULT;
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}
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if (!fault_supports_stage2_pmd_mappings(memslot, hva))
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force_pte = true;
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|
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if (logging_active)
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force_pte = true;
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/* Let's check if we will get back a huge page backed by hugetlbfs */
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down_read(¤t->mm->mmap_sem);
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vma = find_vma_intersection(current->mm, hva, hva + 1);
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@ -1692,6 +1709,12 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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}
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vma_pagesize = vma_kernel_pagesize(vma);
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if (logging_active ||
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!fault_supports_stage2_huge_mapping(memslot, hva, vma_pagesize)) {
|
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force_pte = true;
|
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vma_pagesize = PAGE_SIZE;
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}
|
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|
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/*
|
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* The stage2 has a minimum of 2 level table (For arm64 see
|
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* kvm_arm_setup_stage2()). Hence, we are guaranteed that we can
|
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|
|
@ -1699,11 +1722,9 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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* As for PUD huge maps, we must make sure that we have at least
|
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* 3 levels, i.e, PMD is not folded.
|
||||
*/
|
||||
if ((vma_pagesize == PMD_SIZE ||
|
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(vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm))) &&
|
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!force_pte) {
|
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if (vma_pagesize == PMD_SIZE ||
|
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(vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm)))
|
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gfn = (fault_ipa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT;
|
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}
|
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up_read(¤t->mm->mmap_sem);
|
||||
|
||||
/* We need minimum second+third level pages */
|
||||
|
|
|
|||
|
|
@ -754,8 +754,9 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
|
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u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
|
||||
phys_addr_t base = GITS_BASER_ADDR_48_to_52(baser);
|
||||
int esz = GITS_BASER_ENTRY_SIZE(baser);
|
||||
int index;
|
||||
int index, idx;
|
||||
gfn_t gfn;
|
||||
bool ret;
|
||||
|
||||
switch (type) {
|
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case GITS_BASER_TYPE_DEVICE:
|
||||
|
|
@ -782,7 +783,8 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
|
|||
|
||||
if (eaddr)
|
||||
*eaddr = addr;
|
||||
return kvm_is_visible_gfn(its->dev->kvm, gfn);
|
||||
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* calculate and check the index into the 1st level */
|
||||
|
|
@ -812,7 +814,12 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
|
|||
|
||||
if (eaddr)
|
||||
*eaddr = indirect_ptr;
|
||||
return kvm_is_visible_gfn(its->dev->kvm, gfn);
|
||||
|
||||
out:
|
||||
idx = srcu_read_lock(&its->dev->kvm->srcu);
|
||||
ret = kvm_is_visible_gfn(its->dev->kvm, gfn);
|
||||
srcu_read_unlock(&its->dev->kvm->srcu, idx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int vgic_its_alloc_collection(struct vgic_its *its,
|
||||
|
|
@ -1729,8 +1736,8 @@ static void vgic_its_destroy(struct kvm_device *kvm_dev)
|
|||
kfree(its);
|
||||
}
|
||||
|
||||
int vgic_its_has_attr_regs(struct kvm_device *dev,
|
||||
struct kvm_device_attr *attr)
|
||||
static int vgic_its_has_attr_regs(struct kvm_device *dev,
|
||||
struct kvm_device_attr *attr)
|
||||
{
|
||||
const struct vgic_register_region *region;
|
||||
gpa_t offset = attr->attr;
|
||||
|
|
@ -1750,9 +1757,9 @@ int vgic_its_has_attr_regs(struct kvm_device *dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int vgic_its_attr_regs_access(struct kvm_device *dev,
|
||||
struct kvm_device_attr *attr,
|
||||
u64 *reg, bool is_write)
|
||||
static int vgic_its_attr_regs_access(struct kvm_device *dev,
|
||||
struct kvm_device_attr *attr,
|
||||
u64 *reg, bool is_write)
|
||||
{
|
||||
const struct vgic_register_region *region;
|
||||
struct vgic_its *its;
|
||||
|
|
@ -1919,7 +1926,7 @@ static int vgic_its_save_ite(struct vgic_its *its, struct its_device *dev,
|
|||
((u64)ite->irq->intid << KVM_ITS_ITE_PINTID_SHIFT) |
|
||||
ite->collection->collection_id;
|
||||
val = cpu_to_le64(val);
|
||||
return kvm_write_guest(kvm, gpa, &val, ite_esz);
|
||||
return kvm_write_guest_lock(kvm, gpa, &val, ite_esz);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2066,7 +2073,7 @@ static int vgic_its_save_dte(struct vgic_its *its, struct its_device *dev,
|
|||
(itt_addr_field << KVM_ITS_DTE_ITTADDR_SHIFT) |
|
||||
(dev->num_eventid_bits - 1));
|
||||
val = cpu_to_le64(val);
|
||||
return kvm_write_guest(kvm, ptr, &val, dte_esz);
|
||||
return kvm_write_guest_lock(kvm, ptr, &val, dte_esz);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2246,7 +2253,7 @@ static int vgic_its_save_cte(struct vgic_its *its,
|
|||
((u64)collection->target_addr << KVM_ITS_CTE_RDBASE_SHIFT) |
|
||||
collection->collection_id);
|
||||
val = cpu_to_le64(val);
|
||||
return kvm_write_guest(its->dev->kvm, gpa, &val, esz);
|
||||
return kvm_write_guest_lock(its->dev->kvm, gpa, &val, esz);
|
||||
}
|
||||
|
||||
static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz)
|
||||
|
|
@ -2317,7 +2324,7 @@ static int vgic_its_save_collection_table(struct vgic_its *its)
|
|||
*/
|
||||
val = 0;
|
||||
BUG_ON(cte_esz > sizeof(val));
|
||||
ret = kvm_write_guest(its->dev->kvm, gpa, &val, cte_esz);
|
||||
ret = kvm_write_guest_lock(its->dev->kvm, gpa, &val, cte_esz);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -358,7 +358,7 @@ int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
|
|||
if (status) {
|
||||
/* clear consumed data */
|
||||
val &= ~(1 << bit_nr);
|
||||
ret = kvm_write_guest(kvm, ptr, &val, 1);
|
||||
ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -409,7 +409,7 @@ int vgic_v3_save_pending_tables(struct kvm *kvm)
|
|||
else
|
||||
val &= ~(1 << bit_nr);
|
||||
|
||||
ret = kvm_write_guest(kvm, ptr, &val, 1);
|
||||
ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -867,15 +867,21 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
|
|||
* either observe the new interrupt before or after doing this check,
|
||||
* and introducing additional synchronization mechanism doesn't change
|
||||
* this.
|
||||
*
|
||||
* Note that we still need to go through the whole thing if anything
|
||||
* can be directly injected (GICv4).
|
||||
*/
|
||||
if (list_empty(&vcpu->arch.vgic_cpu.ap_list_head))
|
||||
if (list_empty(&vcpu->arch.vgic_cpu.ap_list_head) &&
|
||||
!vgic_supports_direct_msis(vcpu->kvm))
|
||||
return;
|
||||
|
||||
DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
|
||||
|
||||
raw_spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
|
||||
vgic_flush_lr_state(vcpu);
|
||||
raw_spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
|
||||
if (!list_empty(&vcpu->arch.vgic_cpu.ap_list_head)) {
|
||||
raw_spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
|
||||
vgic_flush_lr_state(vcpu);
|
||||
raw_spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
|
||||
}
|
||||
|
||||
if (can_access_vgic_from_kernel())
|
||||
vgic_restore_state(vcpu);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user