forked from luck/tmp_suning_uos_patched
lightnvm: add support for 2.0 address format
Add support for 2.0 address format. Also, align address bits for 1.2 and 2.0 to be able to operate on channel and luns without requiring a format conversion. Use a generic address format for this purpose. Also, convert the generic operations to the generic format in pblk. Signed-off-by: Javier González <javier@cnexlabs.com> Signed-off-by: Matias Bjørling <mb@lightnvm.io> Signed-off-by: Jens Axboe <axboe@kernel.dk>
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a40afad90b
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6947151374
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@ -194,8 +194,8 @@ static struct nvm_tgt_dev *nvm_create_tgt_dev(struct nvm_dev *dev,
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for (j = 0; j < luns_in_chnl; j++) {
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luns[lunid].ppa = 0;
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luns[lunid].g.ch = i;
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luns[lunid++].g.lun = j;
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luns[lunid].a.ch = i;
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luns[lunid++].a.lun = j;
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lun_offs[j] = blun;
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lun_roffs[j + blun] = blun;
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@ -556,22 +556,22 @@ static void nvm_unregister_map(struct nvm_dev *dev)
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static void nvm_map_to_dev(struct nvm_tgt_dev *tgt_dev, struct ppa_addr *p)
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{
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struct nvm_dev_map *dev_map = tgt_dev->map;
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struct nvm_ch_map *ch_map = &dev_map->chnls[p->g.ch];
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int lun_off = ch_map->lun_offs[p->g.lun];
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struct nvm_ch_map *ch_map = &dev_map->chnls[p->a.ch];
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int lun_off = ch_map->lun_offs[p->a.lun];
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p->g.ch += ch_map->ch_off;
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p->g.lun += lun_off;
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p->a.ch += ch_map->ch_off;
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p->a.lun += lun_off;
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}
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static void nvm_map_to_tgt(struct nvm_tgt_dev *tgt_dev, struct ppa_addr *p)
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{
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struct nvm_dev *dev = tgt_dev->parent;
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struct nvm_dev_map *dev_rmap = dev->rmap;
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struct nvm_ch_map *ch_rmap = &dev_rmap->chnls[p->g.ch];
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int lun_roff = ch_rmap->lun_offs[p->g.lun];
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struct nvm_ch_map *ch_rmap = &dev_rmap->chnls[p->a.ch];
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int lun_roff = ch_rmap->lun_offs[p->a.lun];
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p->g.ch -= ch_rmap->ch_off;
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p->g.lun -= lun_roff;
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p->a.ch -= ch_rmap->ch_off;
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p->a.lun -= lun_roff;
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}
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static void nvm_ppa_tgt_to_dev(struct nvm_tgt_dev *tgt_dev,
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@ -885,7 +885,7 @@ int pblk_line_erase(struct pblk *pblk, struct pblk_line *line)
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}
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ppa = pblk->luns[bit].bppa; /* set ch and lun */
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ppa.g.blk = line->id;
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ppa.a.blk = line->id;
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atomic_dec(&line->left_eblks);
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WARN_ON(test_and_set_bit(bit, line->erase_bitmap));
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@ -1683,8 +1683,8 @@ static void __pblk_down_page(struct pblk *pblk, struct ppa_addr *ppa_list,
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int i;
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for (i = 1; i < nr_ppas; i++)
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WARN_ON(ppa_list[0].g.lun != ppa_list[i].g.lun ||
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ppa_list[0].g.ch != ppa_list[i].g.ch);
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WARN_ON(ppa_list[0].a.lun != ppa_list[i].a.lun ||
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ppa_list[0].a.ch != ppa_list[i].a.ch);
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#endif
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ret = down_timeout(&rlun->wr_sem, msecs_to_jiffies(30000));
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@ -1728,8 +1728,8 @@ void pblk_up_page(struct pblk *pblk, struct ppa_addr *ppa_list, int nr_ppas)
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int i;
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for (i = 1; i < nr_ppas; i++)
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WARN_ON(ppa_list[0].g.lun != ppa_list[i].g.lun ||
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ppa_list[0].g.ch != ppa_list[i].g.ch);
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WARN_ON(ppa_list[0].a.lun != ppa_list[i].a.lun ||
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ppa_list[0].a.ch != ppa_list[i].a.ch);
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#endif
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rlun = &pblk->luns[pos];
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@ -127,7 +127,7 @@ void pblk_map_erase_rq(struct pblk *pblk, struct nvm_rq *rqd,
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atomic_dec(&e_line->left_eblks);
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*erase_ppa = rqd->ppa_list[i];
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erase_ppa->g.blk = e_line->id;
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erase_ppa->a.blk = e_line->id;
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spin_unlock(&e_line->lock);
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@ -168,6 +168,6 @@ void pblk_map_erase_rq(struct pblk *pblk, struct nvm_rq *rqd,
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set_bit(bit, e_line->erase_bitmap);
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atomic_dec(&e_line->left_eblks);
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*erase_ppa = pblk->luns[bit].bppa; /* set ch and lun */
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erase_ppa->g.blk = e_line->id;
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erase_ppa->a.blk = e_line->id;
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}
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}
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@ -39,8 +39,8 @@ static ssize_t pblk_sysfs_luns_show(struct pblk *pblk, char *page)
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sz += snprintf(page + sz, PAGE_SIZE - sz,
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"pblk: pos:%d, ch:%d, lun:%d - %d\n",
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i,
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rlun->bppa.g.ch,
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rlun->bppa.g.lun,
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rlun->bppa.a.ch,
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rlun->bppa.a.lun,
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active);
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}
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@ -936,12 +936,12 @@ static inline int pblk_pad_distance(struct pblk *pblk)
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static inline int pblk_ppa_to_line(struct ppa_addr p)
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{
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return p.g.blk;
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return p.a.blk;
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}
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static inline int pblk_ppa_to_pos(struct nvm_geo *geo, struct ppa_addr p)
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{
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return p.g.lun * geo->num_ch + p.g.ch;
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return p.a.lun * geo->num_ch + p.a.ch;
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}
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static inline struct ppa_addr addr_to_gen_ppa(struct pblk *pblk, u64 paddr,
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@ -16,12 +16,21 @@ enum {
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NVM_IOTYPE_GC = 1,
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};
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#define NVM_BLK_BITS (16)
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#define NVM_PG_BITS (16)
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#define NVM_SEC_BITS (8)
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#define NVM_PL_BITS (8)
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#define NVM_LUN_BITS (8)
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#define NVM_CH_BITS (7)
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/* common format */
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#define NVM_GEN_CH_BITS (8)
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#define NVM_GEN_LUN_BITS (8)
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#define NVM_GEN_BLK_BITS (16)
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#define NVM_GEN_RESERVED (32)
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/* 1.2 format */
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#define NVM_12_PG_BITS (16)
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#define NVM_12_PL_BITS (4)
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#define NVM_12_SEC_BITS (4)
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#define NVM_12_RESERVED (8)
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/* 2.0 format */
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#define NVM_20_SEC_BITS (24)
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#define NVM_20_RESERVED (8)
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enum {
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NVM_OCSSD_SPEC_12 = 12,
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@ -31,16 +40,34 @@ enum {
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struct ppa_addr {
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/* Generic structure for all addresses */
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union {
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/* generic device format */
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struct {
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u64 blk : NVM_BLK_BITS;
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u64 pg : NVM_PG_BITS;
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u64 sec : NVM_SEC_BITS;
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u64 pl : NVM_PL_BITS;
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u64 lun : NVM_LUN_BITS;
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u64 ch : NVM_CH_BITS;
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u64 reserved : 1;
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u64 ch : NVM_GEN_CH_BITS;
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u64 lun : NVM_GEN_LUN_BITS;
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u64 blk : NVM_GEN_BLK_BITS;
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u64 reserved : NVM_GEN_RESERVED;
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} a;
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/* 1.2 device format */
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struct {
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u64 ch : NVM_GEN_CH_BITS;
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u64 lun : NVM_GEN_LUN_BITS;
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u64 blk : NVM_GEN_BLK_BITS;
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u64 pg : NVM_12_PG_BITS;
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u64 pl : NVM_12_PL_BITS;
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u64 sec : NVM_12_SEC_BITS;
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u64 reserved : NVM_12_RESERVED;
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} g;
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/* 2.0 device format */
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struct {
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u64 grp : NVM_GEN_CH_BITS;
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u64 pu : NVM_GEN_LUN_BITS;
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u64 chk : NVM_GEN_BLK_BITS;
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u64 sec : NVM_20_SEC_BITS;
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u64 reserved : NVM_20_RESERVED;
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} m;
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struct {
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u64 line : 63;
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u64 is_cached : 1;
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@ -374,15 +401,25 @@ static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev,
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struct ppa_addr r)
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{
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struct nvm_geo *geo = &tgt_dev->geo;
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struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
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struct ppa_addr l;
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l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
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l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
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l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
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l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
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l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
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l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset;
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if (geo->version == NVM_OCSSD_SPEC_12) {
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struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
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l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
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l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
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l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
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l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
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l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
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l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset;
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} else {
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struct nvm_addrf *lbaf = &geo->addrf;
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l.ppa = ((u64)r.m.grp) << lbaf->ch_offset;
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l.ppa |= ((u64)r.m.pu) << lbaf->lun_offset;
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l.ppa |= ((u64)r.m.chk) << lbaf->chk_offset;
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l.ppa |= ((u64)r.m.sec) << lbaf->sec_offset;
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}
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return l;
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}
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@ -391,17 +428,27 @@ static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev,
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struct ppa_addr r)
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{
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struct nvm_geo *geo = &tgt_dev->geo;
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struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
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struct ppa_addr l;
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l.ppa = 0;
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l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
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l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
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l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
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l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
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l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
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l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
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if (geo->version == NVM_OCSSD_SPEC_12) {
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struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
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l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
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l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
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l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
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l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
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l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
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l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
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} else {
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struct nvm_addrf *lbaf = &geo->addrf;
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l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset;
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l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset;
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l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset;
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l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset;
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}
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return l;
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}
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