forked from luck/tmp_suning_uos_patched
powerpc/e6500: add TMCFG0 register definition
The register is not currently used in the base kernel but will be in a forthcoming kvm patch. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -742,6 +742,12 @@
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#define MMUBE1_VBE4 0x00000002
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#define MMUBE1_VBE5 0x00000001
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#define TMRN_TMCFG0 16 /* Thread Management Configuration Register 0 */
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#define TMRN_TMCFG0_NPRIBITS 0x003f0000 /* Bits of thread priority */
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#define TMRN_TMCFG0_NPRIBITS_SHIFT 16
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#define TMRN_TMCFG0_NATHRD 0x00003f00 /* Number of active threads */
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#define TMRN_TMCFG0_NATHRD_SHIFT 8
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#define TMRN_TMCFG0_NTHRD 0x0000003f /* Number of threads */
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#define TMRN_IMSR0 0x120 /* Initial MSR Register 0 (e6500) */
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#define TMRN_IMSR1 0x121 /* Initial MSR Register 1 (e6500) */
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#define TMRN_INIA0 0x140 /* Next Instruction Address Register 0 */
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