forked from luck/tmp_suning_uos_patched
fsi: master-ast-cf: Add new FSI master using Aspeed ColdFire
The Aspeed AST2x00 can contain a ColdFire v1 coprocessor which is currently unused on OpenPower systems. This adds an alternative to the fsi-master-gpio driver that uses that coprocessor instead of bit banging from the ARM core itself. The end result is about 4 times faster. The firmware for the coprocessor and its source code can be found at https://github.com/ozbenh/cf-fsi and is system specific. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
parent
2be5263c5d
commit
6a794a27da
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@ -27,6 +27,15 @@ config FSI_MASTER_HUB
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allow chaining of FSI links to an arbitrary depth. This allows for
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a high target device fanout.
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config FSI_MASTER_AST_CF
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tristate "FSI master based on Aspeed ColdFire coprocessor"
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depends on GPIOLIB
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depends on GPIO_ASPEED
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---help---
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This option enables a FSI master using the AST2400 and AST2500 GPIO
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lines driven by the internal ColdFire coprocessor. This requires
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the corresponding machine specific ColdFire firmware to be available.
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config FSI_SCOM
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tristate "SCOM FSI client device driver"
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---help---
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@ -2,5 +2,6 @@
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obj-$(CONFIG_FSI) += fsi-core.o
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obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o
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obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o
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obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o
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obj-$(CONFIG_FSI_SCOM) += fsi-scom.o
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obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o
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157
drivers/fsi/cf-fsi-fw.h
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157
drivers/fsi/cf-fsi-fw.h
Normal file
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@ -0,0 +1,157 @@
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// SPDX-License-Identifier: GPL-2.0+
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#ifndef __CF_FSI_FW_H
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#define __CF_FSI_FW_H
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/*
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* uCode file layout
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*
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* 0000...03ff : m68k exception vectors
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* 0400...04ff : Header info & boot config block
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* 0500....... : Code & stack
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*/
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/*
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* Header info & boot config area
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*
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* The Header info is built into the ucode and provide version and
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* platform information.
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*
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* the Boot config needs to be adjusted by the ARM prior to starting
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* the ucode if the Command/Status area isn't at 0x320000 in CF space
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* (ie. beginning of SRAM).
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*/
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#define HDR_OFFSET 0x400
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/* Info: Signature & version */
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#define HDR_SYS_SIG 0x00 /* 2 bytes system signature */
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#define SYS_SIG_SHARED 0x5348
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#define SYS_SIG_SPLIT 0x5350
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#define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */
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#define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */
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#define API_VERSION_MAJ 2 /* Current version */
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#define API_VERSION_MIN 1
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#define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */
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#define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */
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#define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */
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#define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */
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/* Boot Config: Address of Command/Status area */
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#define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */
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#define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */
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#define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */
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#define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
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#define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */
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#define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
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#define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
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#define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
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#define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
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#define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
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#define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
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#define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */
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#define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */
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#define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */
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/*
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* Command/Status area layout: Main part
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*/
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/* Command/Status register:
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*
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* +---------------------------+
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* | STAT | RLEN | CLEN | CMD |
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* | 8 | 8 | 8 | 8 |
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* +---------------------------+
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* | | | |
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* status | | |
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* Response len | |
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* (in bits) | |
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* | |
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* Command len |
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* (in bits) |
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* |
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* Command code
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*
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* Due to the big endian layout, that means that a byte read will
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* return the status byte
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*/
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#define CMD_STAT_REG 0x00
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#define CMD_REG_CMD_MASK 0x000000ff
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#define CMD_REG_CMD_SHIFT 0
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#define CMD_NONE 0x00
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#define CMD_COMMAND 0x01
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#define CMD_BREAK 0x02
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#define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */
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#define CMD_INVALID 0xff
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#define CMD_REG_CLEN_MASK 0x0000ff00
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#define CMD_REG_CLEN_SHIFT 8
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#define CMD_REG_RLEN_MASK 0x00ff0000
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#define CMD_REG_RLEN_SHIFT 16
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#define CMD_REG_STAT_MASK 0xff000000
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#define CMD_REG_STAT_SHIFT 24
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#define STAT_WORKING 0x00
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#define STAT_COMPLETE 0x01
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#define STAT_ERR_INVAL_CMD 0x80
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#define STAT_ERR_INVAL_IRQ 0x81
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#define STAT_ERR_MTOE 0x82
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/* Response tag & CRC */
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#define STAT_RTAG 0x04
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/* Response CRC */
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#define STAT_RCRC 0x05
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/* Echo and Send delay */
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#define ECHO_DLY_REG 0x08
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#define SEND_DLY_REG 0x09
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/* Command data area
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*
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* Last byte of message must be left aligned
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*/
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#define CMD_DATA 0x10 /* 64 bit of data */
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/* Response data area, right aligned, unused top bits are 1 */
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#define RSP_DATA 0x20 /* 32 bit of data */
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/* Misc */
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#define INT_CNT 0x30 /* 32-bit interrupt count */
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#define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */
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#define CF_STARTED 0x38 /* byte, set to -1 when copro started */
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#define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */
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/*
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* SRAM layout: GPIO arbitration part
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*/
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#define ARB_REG 0x40
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#define ARB_ARM_REQ 0x01
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#define ARB_ARM_ACK 0x02
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/* Misc2 */
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#define CF_RESET_D0 0x50
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#define CF_RESET_D1 0x54
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#define BAD_INT_S0 0x58
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#define BAD_INT_S1 0x5c
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#define STOP_CNT 0x60
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/* Internal */
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/*
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* SRAM layout: Trace buffer (debug builds only)
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*/
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#define TRACEBUF 0x100
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#define TR_CLKOBIT0 0xc0
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#define TR_CLKOBIT1 0xc1
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#define TR_CLKOSTART 0x82
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#define TR_OLEN 0x83 /* + len */
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#define TR_CLKZ 0x84 /* + count */
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#define TR_CLKWSTART 0x85
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#define TR_CLKTAG 0x86 /* + tag */
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#define TR_CLKDATA 0x87 /* + len */
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#define TR_CLKCRC 0x88 /* + raw crc */
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#define TR_CLKIBIT0 0x90
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#define TR_CLKIBIT1 0x91
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#define TR_END 0xff
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#endif /* __CF_FSI_FW_H */
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1438
drivers/fsi/fsi-master-ast-cf.c
Normal file
1438
drivers/fsi/fsi-master-ast-cf.c
Normal file
File diff suppressed because it is too large
Load Diff
150
include/trace/events/fsi_master_ast_cf.h
Normal file
150
include/trace/events/fsi_master_ast_cf.h
Normal file
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@ -0,0 +1,150 @@
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM fsi_master_ast_cf
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#if !defined(_TRACE_FSI_MASTER_ACF_H) || defined(TRACE_HEADER_MULTI_READ)
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#define _TRACE_FSI_MASTER_ACF_H
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#include <linux/tracepoint.h>
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TRACE_EVENT(fsi_master_acf_copro_command,
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TP_PROTO(const struct fsi_master_acf *master, uint32_t op),
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TP_ARGS(master, op),
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TP_STRUCT__entry(
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__field(int, master_idx)
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__field(uint32_t, op)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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__entry->op = op;
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),
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TP_printk("fsi-acf%d command %08x",
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__entry->master_idx, __entry->op
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)
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);
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TRACE_EVENT(fsi_master_acf_send_request,
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TP_PROTO(const struct fsi_master_acf *master, const struct fsi_msg *cmd, u8 rbits),
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TP_ARGS(master, cmd, rbits),
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TP_STRUCT__entry(
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__field(int, master_idx)
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__field(uint64_t, msg)
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__field(u8, bits)
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__field(u8, rbits)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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__entry->msg = cmd->msg;
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__entry->bits = cmd->bits;
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__entry->rbits = rbits;
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),
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TP_printk("fsi-acf%d cmd: %016llx/%d/%d",
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__entry->master_idx, (unsigned long long)__entry->msg,
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__entry->bits, __entry->rbits
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)
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);
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TRACE_EVENT(fsi_master_acf_copro_response,
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TP_PROTO(const struct fsi_master_acf *master, u8 rtag, u8 rcrc, __be32 rdata, bool crc_ok),
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TP_ARGS(master, rtag, rcrc, rdata, crc_ok),
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TP_STRUCT__entry(
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__field(int, master_idx)
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__field(u8, rtag)
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__field(u8, rcrc)
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__field(u32, rdata)
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__field(bool, crc_ok)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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__entry->rtag = rtag;
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__entry->rcrc = rcrc;
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__entry->rdata = be32_to_cpu(rdata);
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__entry->crc_ok = crc_ok;
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),
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TP_printk("fsi-acf%d rsp: tag=%04x crc=%04x data=%08x %c\n",
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__entry->master_idx, __entry->rtag, __entry->rcrc,
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__entry->rdata, __entry->crc_ok ? ' ' : '!'
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)
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);
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TRACE_EVENT(fsi_master_acf_crc_rsp_error,
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TP_PROTO(const struct fsi_master_acf *master, int retries),
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TP_ARGS(master, retries),
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TP_STRUCT__entry(
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__field(int, master_idx)
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__field(int, retries)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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__entry->retries = retries;
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),
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TP_printk("fsi-acf%d CRC error in response retry %d",
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__entry->master_idx, __entry->retries
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)
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);
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TRACE_EVENT(fsi_master_acf_poll_response_busy,
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TP_PROTO(const struct fsi_master_acf *master, int busy_count),
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TP_ARGS(master, busy_count),
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TP_STRUCT__entry(
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__field(int, master_idx)
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__field(int, busy_count)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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__entry->busy_count = busy_count;
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),
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TP_printk("fsi-acf%d: device reported busy %d times",
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__entry->master_idx, __entry->busy_count
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)
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);
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TRACE_EVENT(fsi_master_acf_cmd_abs_addr,
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TP_PROTO(const struct fsi_master_acf *master, u32 addr),
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TP_ARGS(master, addr),
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TP_STRUCT__entry(
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__field(int, master_idx)
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__field(u32, addr)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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__entry->addr = addr;
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),
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TP_printk("fsi-acf%d: Sending ABS_ADR %06x",
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__entry->master_idx, __entry->addr
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)
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);
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TRACE_EVENT(fsi_master_acf_cmd_rel_addr,
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TP_PROTO(const struct fsi_master_acf *master, u32 rel_addr),
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TP_ARGS(master, rel_addr),
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TP_STRUCT__entry(
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__field(int, master_idx)
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__field(u32, rel_addr)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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__entry->rel_addr = rel_addr;
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),
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TP_printk("fsi-acf%d: Sending REL_ADR %03x",
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__entry->master_idx, __entry->rel_addr
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)
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);
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TRACE_EVENT(fsi_master_acf_cmd_same_addr,
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TP_PROTO(const struct fsi_master_acf *master),
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TP_ARGS(master),
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TP_STRUCT__entry(
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__field(int, master_idx)
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),
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TP_fast_assign(
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__entry->master_idx = master->master.idx;
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),
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TP_printk("fsi-acf%d: Sending SAME_ADR",
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__entry->master_idx
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)
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);
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#endif /* _TRACE_FSI_MASTER_ACF_H */
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#include <trace/define_trace.h>
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