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clk: fractional-divider: support for divider bypassing

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If the divider or multiplier values are 0 in the register, bypassing the
divider and returning the parent clock rate in clk_fd_recalc_rate().

Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed commitlog typo]
This commit is contained in:
Heikki Krogerus 2015-02-02 15:37:04 +02:00 committed by Stephen Boyd
parent 496eadf821
commit 6b54783620
1 changed files with 3 additions and 0 deletions
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drivers/clk/clk-fractional-divider.c
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@ -36,6 +36,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
if (!n || !m)
return parent_rate;
ret = (u64)parent_rate * m;
do_div(ret, n);