forked from luck/tmp_suning_uos_patched
ARM: Integrator: move 16-bit timer support to Integrator/AP
Only Integrator/AP has 16-bit timers, so move the support into the Integrator/AP specific support files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
5a46334ac6
commit
6be4826e37
@ -1 +0,0 @@
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extern void integrator_time_init(u32, unsigned int);
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@ -19,8 +19,6 @@
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#include <linux/termios.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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@ -28,14 +26,11 @@
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/irq.h>
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#include <asm/hardware/arm_timer.h>
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#include <mach/cm.h>
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#include <asm/system.h>
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#include <asm/leds.h>
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#include <asm/mach/time.h>
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#include "common.h"
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static struct amba_pl010_data integrator_uart_data;
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static struct amba_device rtc_device = {
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@ -220,155 +215,3 @@ void cm_control(u32 mask, u32 set)
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}
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EXPORT_SYMBOL(cm_control);
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
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#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
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#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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static unsigned long timer_reload;
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static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
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static cycle_t timersp_read(struct clocksource *cs)
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{
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return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
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}
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static struct clocksource clocksource_timersp = {
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.name = "timer2",
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.rating = 200,
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.read = timersp_read,
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.mask = CLOCKSOURCE_MASK(16),
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.shift = 16,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void integrator_clocksource_init(u32 khz)
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{
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struct clocksource *cs = &clocksource_timersp;
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void __iomem *base = clksrc_base;
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u32 ctrl = TIMER_CTRL_ENABLE;
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if (khz >= 1500) {
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khz /= 16;
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ctrl = TIMER_CTRL_DIV16;
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}
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writel(ctrl, base + TIMER_CTRL);
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writel(0xffff, base + TIMER_LOAD);
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cs->mult = clocksource_khz2mult(khz, cs->shift);
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clocksource_register(cs);
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}
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static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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writel(ctrl, clkevt_base + TIMER_CTRL);
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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}
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writel(ctrl, clkevt_base + TIMER_CTRL);
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.shift = 34,
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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.cpumask = cpu_all_mask,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(u32 khz, unsigned int ctrl)
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{
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struct clock_event_device *evt = &integrator_clockevent;
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if (khz * 1000 > 0x100000 * HZ) {
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khz /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (khz * 1000 > 0x10000 * HZ) {
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khz /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = khz * 1000 / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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evt->irq = IRQ_TIMERINT1;
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evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
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evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
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setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
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clockevents_register_device(evt);
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}
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/*
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* Set up timer(s).
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*/
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void __init integrator_time_init(u32 khz, unsigned int ctrl)
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{
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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integrator_clocksource_init(khz);
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integrator_clockevent_init(khz, ctrl);
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}
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@ -27,10 +27,14 @@
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#include <linux/sysdev.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/param.h> /* HZ */
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@ -44,8 +48,6 @@
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "common.h"
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/*
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* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
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* is the (PA >> 12).
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@ -335,9 +337,159 @@ static void __init ap_init(void)
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}
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}
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
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#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
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#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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static unsigned long timer_reload;
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static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
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static cycle_t timersp_read(struct clocksource *cs)
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{
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return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
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}
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static struct clocksource clocksource_timersp = {
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.name = "timer2",
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.rating = 200,
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.read = timersp_read,
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.mask = CLOCKSOURCE_MASK(16),
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.shift = 16,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void integrator_clocksource_init(u32 khz)
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{
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struct clocksource *cs = &clocksource_timersp;
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void __iomem *base = clksrc_base;
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u32 ctrl = TIMER_CTRL_ENABLE;
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if (khz >= 1500) {
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khz /= 16;
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ctrl = TIMER_CTRL_DIV16;
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}
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writel(ctrl, base + TIMER_CTRL);
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writel(0xffff, base + TIMER_LOAD);
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cs->mult = clocksource_khz2mult(khz, cs->shift);
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clocksource_register(cs);
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}
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static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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writel(ctrl, clkevt_base + TIMER_CTRL);
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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}
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writel(ctrl, clkevt_base + TIMER_CTRL);
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.shift = 34,
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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.cpumask = cpu_all_mask,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(u32 khz)
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{
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struct clock_event_device *evt = &integrator_clockevent;
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unsigned int ctrl = 0;
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if (khz * 1000 > 0x100000 * HZ) {
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khz /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (khz * 1000 > 0x10000 * HZ) {
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khz /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = khz * 1000 / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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evt->irq = IRQ_TIMERINT1;
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evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
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evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
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setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
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clockevents_register_device(evt);
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}
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/*
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* Set up timer(s).
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*/
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static void __init ap_init_timer(void)
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{
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integrator_time_init(TICKS_PER_uSEC * 1000, 0);
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u32 khz = TICKS_PER_uSEC * 1000;
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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integrator_clocksource_init(khz);
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integrator_clockevent_init(khz);
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}
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static struct sys_timer ap_timer = {
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@ -43,8 +43,6 @@
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#include <plat/timer-sp.h>
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#include "common.h"
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#define INTCP_PA_FLASH_BASE 0x24000000
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#define INTCP_FLASH_SIZE SZ_32M
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