forked from luck/tmp_suning_uos_patched
sh: add SH7760 IPR IRQ data
Add SH7760 IPR IRQ data; makes 2.6.20-rc bootable again. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Manuel Lauss
Paul Mundt
parent
86b67ef751
commit
6dcda6f1ec
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@ -52,17 +52,11 @@ static int __init sh7760_devices_setup(void)
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}
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__initcall(sh7760_devices_setup);
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/*
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* SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
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*/
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static struct intc2_data intc2_irq_table[] = {
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/* INTPRIO0 | INTMSK0 */
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{48, 0, 28, 0, 31, 3}, /* IRQ 4 */
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{49, 0, 24, 0, 30, 3}, /* IRQ 3 */
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{50, 0, 20, 0, 29, 3}, /* IRQ 2 */
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{51, 0, 16, 0, 28, 3}, /* IRQ 1 */
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/* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
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/* INTPRIO4 | INTMSK0 */
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{56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
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{57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
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{58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
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@ -71,18 +65,15 @@ static struct intc2_data intc2_irq_table[] = {
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{61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
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{62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
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{63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
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/* INTPRIO8 | INTMSK0 */
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{52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
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{53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
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{54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
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{55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
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{64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
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{65, 8, 24, 0, 16, 3}, /* LCDC */
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/* 66, 67 unused */
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{68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
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{69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
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{70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
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/* 71 unused */
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{72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
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{73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
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{74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
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@ -91,26 +82,71 @@ static struct intc2_data intc2_irq_table[] = {
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{77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
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{78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
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{79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
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/* | INTMSK4 */
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{80, 8, 4, 4, 23, 3}, /* SIM_ERI */
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{81, 8, 4, 4, 22, 3}, /* SIM_RXI */
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{82, 8, 4, 4, 21, 3}, /* SIM_TXI */
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{83, 8, 4, 4, 20, 3}, /* SIM_TEI */
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{84, 8, 0, 4, 19, 3}, /* HSPII */
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/* INTPRIOC | INTMSK4 */
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/* 85-87 unused/reserved */
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{88, 12, 20, 4, 18, 3}, /* MMCI0 */
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{89, 12, 20, 4, 17, 3}, /* MMCI1 */
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{90, 12, 20, 4, 16, 3}, /* MMCI2 */
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{91, 12, 20, 4, 15, 3}, /* MMCI3 */
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{92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
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/* 93-107 reserved/undocumented */
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{92, 12, 12, 4, 6, 3}, /* MFI */
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{108,12, 4, 4, 1, 3}, /* ADC */
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{109,12, 0, 4, 0, 3}, /* CMTI */
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/* 110-111 reserved/unused */
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};
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static struct ipr_data sh7760_ipr_map[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 8, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 19, 0, 4, 2 }, /* TMU2 TIPCI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 28, 1, 8, 2 }, /* REF RCMI */
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{ 29, 1, 8, 2 }, /* REF ROVI */
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{ 32, 2, 0, 7 }, /* HUDI */
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{ 33, 2, 12, 7 }, /* GPIOI */
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{ 34, 2, 8, 7 }, /* DMAC DMTE0 */
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{ 35, 2, 8, 7 }, /* DMAC DMTE1 */
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{ 36, 2, 8, 7 }, /* DMAC DMTE2 */
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{ 37, 2, 8, 7 }, /* DMAC DMTE3 */
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{ 38, 2, 8, 7 }, /* DMAC DMAE */
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{ 44, 2, 8, 7 }, /* DMAC DMTE4 */
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{ 45, 2, 8, 7 }, /* DMAC DMTE5 */
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{ 46, 2, 8, 7 }, /* DMAC DMTE6 */
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{ 47, 2, 8, 7 }, /* DMAC DMTE7 */
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/* these here are only valid if INTC_ICR bit 7 is set to 1!
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* XXX: maybe CONFIG_SH_IRLMODE symbol? SH7751 could use it too */
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#if 0
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{ 2, 3, 12, 3 }, /* IRL0 */
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{ 5, 3, 8, 3 }, /* IRL1 */
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{ 8, 3, 4, 3 }, /* IRL2 */
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{ 11, 3, 0, 3 }, /* IRL3 */
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#endif
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};
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static unsigned long ipr_offsets[] = {
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0xffd00004UL, /* 0: IPRA */
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0xffd00008UL, /* 1: IPRB */
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0xffd0000cUL, /* 2: IPRC */
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0xffd00010UL, /* 3: IPRD */
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};
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/* given the IPR index return the address of the IPR register */
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unsigned int map_ipridx_to_addr(int idx)
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{
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if (idx >= ARRAY_SIZE(ipr_offsets))
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return 0;
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return ipr_offsets[idx];
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}
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void __init init_IRQ_intc2(void)
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{
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make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
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}
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void __init init_IRQ_ipr(void)
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{
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make_ipr_irq(sh7760_ipr_map, ARRAY_SIZE(sh7760_ipr_map));
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}
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@ -151,6 +151,7 @@ config CPU_SUBTYPE_SH7760
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bool "Support SH7760 processor"
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select CPU_SH4
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select CPU_HAS_INTC2_IRQ
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select CPU_HAS_IPR_IRQ
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config CPU_SUBTYPE_SH4_202
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bool "Support SH4-202 processor"
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