forked from luck/tmp_suning_uos_patched
soc/tegra: fuse: Add RAM code reader helper
Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -28,8 +28,15 @@
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#define APBMISC_SIZE 0x64
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#define FUSE_SKU_INFO 0x10
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#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
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#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
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(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
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#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
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(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
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static void __iomem *apbmisc_base;
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static void __iomem *strapping_base;
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static bool long_ram_code;
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u32 tegra_read_chipid(void)
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{
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@ -54,6 +61,18 @@ u32 tegra_read_straps(void)
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return 0;
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}
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u32 tegra_read_ram_code(void)
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{
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u32 straps = tegra_read_straps();
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if (long_ram_code)
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straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
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else
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straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
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return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
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}
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static const struct of_device_id apbmisc_match[] __initconst = {
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{ .compatible = "nvidia,tegra20-apbmisc", },
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{},
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@ -112,4 +131,6 @@ void __init tegra_init_apbmisc(void)
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strapping_base = of_iomap(np, 1);
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if (!strapping_base)
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pr_err("ioremap tegra strapping_base failed\n");
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long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
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}
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@ -56,6 +56,7 @@ struct tegra_sku_info {
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};
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u32 tegra_read_straps(void);
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u32 tegra_read_ram_code(void);
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u32 tegra_read_chipid(void);
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int tegra_fuse_readl(unsigned long offset, u32 *value);
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