forked from luck/tmp_suning_uos_patched
MIPS: Loongson: Add basic Loongson 2F support
Loongson 2F has built-in DDR2 and PCI-X controller. The PCI-X controller has a programming interface similiar to the the FPGA northbridge used on Loongson 2E. The main differences between Loongson 2E and Loongson 2F include: 1. Loongson 2F has an extra address window configuration module, which is used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space. 2. Loongson 2F supports 8 levels of software configurable CPu frequency which can be configured in the LOONGSON_CHIPCFG0 register. The coming cpufreq and standby support are based on this feature. Loongson.h abstracts the modules and corresponding methods are abstracted. Add other Loongson-2F-specific source code including gcc 4.4 support, PCI memory space, PCI IO space, DMA address. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Wu Zhangjin
Ralf Baechle
parent
937893cf5b
commit
6f7a251a25
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@ -1073,6 +1073,21 @@ config CPU_LOONGSON2E
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The Loongson 2E processor implements the MIPS III instruction set
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with many extensions.
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It has an internal FPGA northbridge, which is compatiable to
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bonito64.
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config CPU_LOONGSON2F
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bool "Loongson 2F"
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depends on SYS_HAS_CPU_LOONGSON2F
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select CPU_LOONGSON2
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help
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The Loongson 2F processor implements the MIPS III instruction set
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with many extensions.
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Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
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have a similar programming interface with FPGA northbridge used in
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Loongson2E.
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config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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depends on SYS_HAS_CPU_MIPS32_R1
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@ -1317,6 +1332,9 @@ config CPU_LOONGSON2
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config SYS_HAS_CPU_LOONGSON2E
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bool
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config SYS_HAS_CPU_LOONGSON2F
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bool
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config SYS_HAS_CPU_MIPS32_R1
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bool
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@ -125,6 +125,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
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cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
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cflags-$(CONFIG_CPU_LOONGSON2E) += \
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$(call cc-option,-march=loongson2e,-march=r4600)
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cflags-$(CONFIG_CPU_LOONGSON2F) += \
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$(call cc-option,-march=loongson2f,-march=r4600)
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cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
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-Wa,-mips32 -Wa,--trap
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@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
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static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
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dma_addr_t dma_addr)
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{
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#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
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return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
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#else
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return dma_addr & 0x7fffffff;
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#endif
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}
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static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin <wuzj@lemote.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -219,4 +219,86 @@ extern void mach_irq_dispatch(unsigned int pending);
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#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
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((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
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/* Chip Config */
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#ifdef CONFIG_CPU_LOONGSON2F
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#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
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#endif
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/*
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* address windows configuration module
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*
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* loongson2e do not have this module
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*/
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#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
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/* address window config module base address */
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#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
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#define LOONGSON_ADDRWINCFG_SIZE 0x180
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extern unsigned long _loongson_addrwincfg_base;
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#define LOONGSON_ADDRWINCFG(offset) \
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(*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
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#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
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#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
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#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
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#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
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#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
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#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
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#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
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#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
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#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
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#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
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#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
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#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
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#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
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#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
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#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
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#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
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#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
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#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
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#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
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#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
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#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
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#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
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#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
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#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
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#define ADDRWIN_WIN0 0
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#define ADDRWIN_WIN1 1
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#define ADDRWIN_WIN2 2
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#define ADDRWIN_WIN3 3
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#define ADDRWIN_MAP_DST_DDR 0
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#define ADDRWIN_MAP_DST_PCI 1
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#define ADDRWIN_MAP_DST_LIO 1
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/*
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* s: CPU, PCIDMA
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* d: DDR, PCI, LIO
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* win: 0, 1, 2, 3
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* src: map source
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* dst: map destination
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* size: ~mask + 1
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*/
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#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
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s##_WIN##w##_BASE = (src); \
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s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
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s##_WIN##w##_MASK = ~(size-1); \
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} while (0)
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#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
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LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
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#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
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LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
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#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
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LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
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#endif /* ! CONFIG_CPU_LOONGSON2F && CONFIG_64BIT */
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#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin <wuzj@lemote.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -12,19 +12,30 @@
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#define __ASM_MACH_LOONGSON_MEM_H
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/*
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* On Lemote Loongson 2e
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* high memory space
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*
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* the high memory space starts from 512M.
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* the peripheral registers reside between 0x1000:0000 and 0x2000:0000.
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* in loongson2e, starts from 512M
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* in loongson2f, starts from 2G 256M
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*/
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#ifdef CONFIG_CPU_LOONGSON2E
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#define LOONGSON_HIGHMEM_START 0x20000000
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#else
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#define LOONGSON_HIGHMEM_START 0x90000000
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#endif
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/*
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* the peripheral registers(MMIO):
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*
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* On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
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* On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
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*/
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#ifdef CONFIG_LEMOTE_FULOONG2E
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#define LOONGSON_HIGHMEM_START 0x20000000
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#define LOONGSON_MMIO_MEM_START 0x10000000
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#define LOONGSON_MMIO_MEM_END 0x20000000
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#ifdef CONFIG_CPU_LOONGSON2E
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#define LOONGSON_MMIO_MEM_END 0x20000000
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#else
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#define LOONGSON_MMIO_MEM_END 0x80000000
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#endif
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#endif /* __ASM_MACH_LOONGSON_MEM_H */
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
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* Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
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*
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* This program is free software; you can redistribute it
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* and/or modify it under the terms of the GNU General
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@ -24,7 +25,30 @@
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extern struct pci_ops loongson_pci_ops;
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#ifdef CONFIG_LEMOTE_FULOONG2E
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/* this is an offset from mips_io_port_base */
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#define LOONGSON_PCI_IO_START 0x00004000UL
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#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
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/*
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* we use address window2 to map cpu address space to pci space
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* window2: cpu [1G, 2G] -> pci [1G, 2G]
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* why not use window 0 & 1? because they are used by cpu when booting.
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* window0: cpu [0, 256M] -> ddr [0, 256M]
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* window1: cpu [256M, 512M] -> pci [256M, 512M]
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*/
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/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
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#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
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#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
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#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
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#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
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#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
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LOONGSON_PCI_MEM_START + 1)
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#else /* loongson2f/32bit & loongson2e */
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/* this pci memory space is mapped by pcimap in pci.c */
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#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
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@ -32,6 +56,6 @@ extern struct pci_ops loongson_pci_ops;
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/* this is an offset from mips_io_port_base */
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#define LOONGSON_PCI_IO_START 0x00004000UL
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#endif
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#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/
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#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
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@ -12,6 +12,7 @@
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* option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/compiler.h>
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#include <loongson.h>
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@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = {
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.unmask = bonito_irq_enable,
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};
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static struct irqaction dma_timeout_irqaction = {
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static struct irqaction __maybe_unused dma_timeout_irqaction = {
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.handler = no_action,
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.name = "dma_timeout",
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};
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@ -47,5 +48,7 @@ void bonito_irq_init(void)
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for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
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set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
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#ifdef CONFIG_CPU_LOONGSON2E
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setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
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#endif
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}
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@ -12,12 +12,20 @@
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#include <loongson.h>
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/* Loongson CPU address windows config space base address */
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unsigned long __maybe_unused _loongson_addrwincfg_base;
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void __init prom_init(void)
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{
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/* init base address of io space */
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set_io_port_base((unsigned long)
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ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
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#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
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_loongson_addrwincfg_base = (unsigned long)
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ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
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#endif
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prom_init_cmdline();
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prom_init_env();
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prom_init_memory();
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@ -21,14 +21,31 @@ void __init prom_init_memory(void)
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add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
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20), BOOT_MEM_RESERVED);
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#ifdef CONFIG_64BIT
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if (highmemsize > 0)
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add_memory_region(LOONGSON_HIGHMEM_START,
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highmemsize << 20, BOOT_MEM_RAM);
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#ifdef CONFIG_CPU_LOONGSON2F
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{
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int bit;
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add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
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LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
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bit = fls(memsize + highmemsize);
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if (bit != ffs(memsize + highmemsize))
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bit += 20;
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else
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bit = bit + 20 - 1;
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#endif /* CONFIG_64BIT */
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/* set cpu window3 to map CPU to DDR: 2G -> 2G */
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LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul,
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0x80000000ul, (1 << bit));
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mmiowb();
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}
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#endif /* CONFIG_CPU_LOONGSON2F */
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if (highmemsize > 0)
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add_memory_region(LOONGSON_HIGHMEM_START,
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highmemsize << 20, BOOT_MEM_RAM);
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add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
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LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
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#endif /* CONFIG_64BIT */
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}
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/* override of arch/mips/mm/cache.c: __uncached_access */
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@ -67,6 +67,14 @@ static void __init setup_pcimap(void)
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/* can not change gnt to break pci transfer when device's gnt not
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deassert for some broken device */
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LOONGSON_PXARB_CFG = 0x00fe0105ul;
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#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
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/*
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* set cpu addr window2 to map CPU address space to PCI address space
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*/
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LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
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LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
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#endif
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}
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static int __init pcibios_init(void)
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