forked from luck/tmp_suning_uos_patched
net/mlx4_en: Add QCN parameters and statistics handling
Implement the IEEE DCB handlers for set/get QCN parameters and statistics reading per TC. Signed-off-by: Shani Michaeli <shanim@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shani Michaeli
David S. Miller
parent
d237baa1cb
commit
708b869bf5
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@ -36,6 +36,49 @@
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#include "mlx4_en.h"
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/* Definitions for QCN
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*/
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struct mlx4_congestion_control_mb_prio_802_1_qau_params {
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__be32 modify_enable_high;
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__be32 modify_enable_low;
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__be32 reserved1;
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__be32 extended_enable;
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__be32 rppp_max_rps;
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__be32 rpg_time_reset;
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__be32 rpg_byte_reset;
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__be32 rpg_threshold;
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__be32 rpg_max_rate;
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__be32 rpg_ai_rate;
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__be32 rpg_hai_rate;
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__be32 rpg_gd;
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__be32 rpg_min_dec_fac;
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__be32 rpg_min_rate;
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__be32 max_time_rise;
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__be32 max_byte_rise;
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__be32 max_qdelta;
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__be32 min_qoffset;
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__be32 gd_coefficient;
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__be32 reserved2[5];
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__be32 cp_sample_base;
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__be32 reserved3[39];
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};
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struct mlx4_congestion_control_mb_prio_802_1_qau_statistics {
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__be64 rppp_rp_centiseconds;
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__be32 reserved1;
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__be32 ignored_cnm;
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__be32 rppp_created_rps;
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__be32 estimated_total_rate;
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__be32 max_active_rate_limiter_index;
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__be32 dropped_cnms_busy_fw;
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__be32 reserved2;
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__be32 cnms_handled_successfully;
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__be32 min_total_limiters_rate;
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__be32 max_total_limiters_rate;
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__be32 reserved3[4];
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};
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static int mlx4_en_dcbnl_ieee_getets(struct net_device *dev,
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struct ieee_ets *ets)
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{
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@ -242,6 +285,178 @@ static int mlx4_en_dcbnl_ieee_setmaxrate(struct net_device *dev,
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return 0;
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}
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#define RPG_ENABLE_BIT 31
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#define CN_TAG_BIT 30
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static int mlx4_en_dcbnl_ieee_getqcn(struct net_device *dev,
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struct ieee_qcn *qcn)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_congestion_control_mb_prio_802_1_qau_params *hw_qcn;
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struct mlx4_cmd_mailbox *mailbox_out = NULL;
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u64 mailbox_in_dma = 0;
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u32 inmod = 0;
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int i, err;
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if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QCN))
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return -EOPNOTSUPP;
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mailbox_out = mlx4_alloc_cmd_mailbox(priv->mdev->dev);
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if (IS_ERR(mailbox_out))
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return -ENOMEM;
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hw_qcn =
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(struct mlx4_congestion_control_mb_prio_802_1_qau_params *)
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mailbox_out->buf;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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inmod = priv->port | ((1 << i) << 8) |
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(MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT << 16);
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err = mlx4_cmd_box(priv->mdev->dev, mailbox_in_dma,
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mailbox_out->dma,
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inmod, MLX4_CONGESTION_CONTROL_GET_PARAMS,
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MLX4_CMD_CONGESTION_CTRL_OPCODE,
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MLX4_CMD_TIME_CLASS_C,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
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return err;
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}
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qcn->rpg_enable[i] =
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be32_to_cpu(hw_qcn->extended_enable) >> RPG_ENABLE_BIT;
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qcn->rppp_max_rps[i] =
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be32_to_cpu(hw_qcn->rppp_max_rps);
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qcn->rpg_time_reset[i] =
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be32_to_cpu(hw_qcn->rpg_time_reset);
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qcn->rpg_byte_reset[i] =
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be32_to_cpu(hw_qcn->rpg_byte_reset);
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qcn->rpg_threshold[i] =
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be32_to_cpu(hw_qcn->rpg_threshold);
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qcn->rpg_max_rate[i] =
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be32_to_cpu(hw_qcn->rpg_max_rate);
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qcn->rpg_ai_rate[i] =
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be32_to_cpu(hw_qcn->rpg_ai_rate);
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qcn->rpg_hai_rate[i] =
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be32_to_cpu(hw_qcn->rpg_hai_rate);
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qcn->rpg_gd[i] =
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be32_to_cpu(hw_qcn->rpg_gd);
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qcn->rpg_min_dec_fac[i] =
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be32_to_cpu(hw_qcn->rpg_min_dec_fac);
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qcn->rpg_min_rate[i] =
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be32_to_cpu(hw_qcn->rpg_min_rate);
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qcn->cndd_state_machine[i] =
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priv->cndd_state[i];
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}
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
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return 0;
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}
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static int mlx4_en_dcbnl_ieee_setqcn(struct net_device *dev,
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struct ieee_qcn *qcn)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_congestion_control_mb_prio_802_1_qau_params *hw_qcn;
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struct mlx4_cmd_mailbox *mailbox_in = NULL;
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u64 mailbox_in_dma = 0;
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u32 inmod = 0;
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int i, err;
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#define MODIFY_ENABLE_HIGH_MASK 0xc0000000
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#define MODIFY_ENABLE_LOW_MASK 0xffc00000
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if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QCN))
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return -EOPNOTSUPP;
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mailbox_in = mlx4_alloc_cmd_mailbox(priv->mdev->dev);
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if (IS_ERR(mailbox_in))
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return -ENOMEM;
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mailbox_in_dma = mailbox_in->dma;
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hw_qcn =
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(struct mlx4_congestion_control_mb_prio_802_1_qau_params *)mailbox_in->buf;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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inmod = priv->port | ((1 << i) << 8) |
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(MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT << 16);
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/* Before updating QCN parameter,
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* need to set it's modify enable bit to 1
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*/
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hw_qcn->modify_enable_high = cpu_to_be32(
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MODIFY_ENABLE_HIGH_MASK);
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hw_qcn->modify_enable_low = cpu_to_be32(MODIFY_ENABLE_LOW_MASK);
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hw_qcn->extended_enable = cpu_to_be32(qcn->rpg_enable[i] << RPG_ENABLE_BIT);
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hw_qcn->rppp_max_rps = cpu_to_be32(qcn->rppp_max_rps[i]);
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hw_qcn->rpg_time_reset = cpu_to_be32(qcn->rpg_time_reset[i]);
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hw_qcn->rpg_byte_reset = cpu_to_be32(qcn->rpg_byte_reset[i]);
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hw_qcn->rpg_threshold = cpu_to_be32(qcn->rpg_threshold[i]);
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hw_qcn->rpg_max_rate = cpu_to_be32(qcn->rpg_max_rate[i]);
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hw_qcn->rpg_ai_rate = cpu_to_be32(qcn->rpg_ai_rate[i]);
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hw_qcn->rpg_hai_rate = cpu_to_be32(qcn->rpg_hai_rate[i]);
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hw_qcn->rpg_gd = cpu_to_be32(qcn->rpg_gd[i]);
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hw_qcn->rpg_min_dec_fac = cpu_to_be32(qcn->rpg_min_dec_fac[i]);
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hw_qcn->rpg_min_rate = cpu_to_be32(qcn->rpg_min_rate[i]);
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priv->cndd_state[i] = qcn->cndd_state_machine[i];
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if (qcn->cndd_state_machine[i] == DCB_CNDD_INTERIOR_READY)
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hw_qcn->extended_enable |= cpu_to_be32(1 << CN_TAG_BIT);
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err = mlx4_cmd(priv->mdev->dev, mailbox_in_dma, inmod,
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MLX4_CONGESTION_CONTROL_SET_PARAMS,
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MLX4_CMD_CONGESTION_CTRL_OPCODE,
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MLX4_CMD_TIME_CLASS_C,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_in);
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return err;
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}
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}
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_in);
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return 0;
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}
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static int mlx4_en_dcbnl_ieee_getqcnstats(struct net_device *dev,
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struct ieee_qcn_stats *qcn_stats)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_congestion_control_mb_prio_802_1_qau_statistics *hw_qcn_stats;
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struct mlx4_cmd_mailbox *mailbox_out = NULL;
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u64 mailbox_in_dma = 0;
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u32 inmod = 0;
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int i, err;
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if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QCN))
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return -EOPNOTSUPP;
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mailbox_out = mlx4_alloc_cmd_mailbox(priv->mdev->dev);
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if (IS_ERR(mailbox_out))
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return -ENOMEM;
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hw_qcn_stats =
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(struct mlx4_congestion_control_mb_prio_802_1_qau_statistics *)
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mailbox_out->buf;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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inmod = priv->port | ((1 << i) << 8) |
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(MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT << 16);
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err = mlx4_cmd_box(priv->mdev->dev, mailbox_in_dma,
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mailbox_out->dma, inmod,
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MLX4_CONGESTION_CONTROL_GET_STATISTICS,
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MLX4_CMD_CONGESTION_CTRL_OPCODE,
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MLX4_CMD_TIME_CLASS_C,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
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return err;
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}
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qcn_stats->rppp_rp_centiseconds[i] =
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be64_to_cpu(hw_qcn_stats->rppp_rp_centiseconds);
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qcn_stats->rppp_created_rps[i] =
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be32_to_cpu(hw_qcn_stats->rppp_created_rps);
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}
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
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return 0;
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}
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const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops = {
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.ieee_getets = mlx4_en_dcbnl_ieee_getets,
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.ieee_setets = mlx4_en_dcbnl_ieee_setets,
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@ -252,6 +467,9 @@ const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops = {
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.getdcbx = mlx4_en_dcbnl_getdcbx,
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.setdcbx = mlx4_en_dcbnl_setdcbx,
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.ieee_getqcn = mlx4_en_dcbnl_ieee_getqcn,
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.ieee_setqcn = mlx4_en_dcbnl_ieee_setqcn,
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.ieee_getqcnstats = mlx4_en_dcbnl_ieee_getqcnstats,
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};
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const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops = {
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@ -608,6 +608,7 @@ struct mlx4_en_priv {
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#ifdef CONFIG_MLX4_EN_DCB
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struct ieee_ets ets;
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u16 maxrate[IEEE_8021QAZ_MAX_TCS];
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enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
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#endif
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#ifdef CONFIG_RFS_ACCEL
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spinlock_t filters_lock;
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