forked from luck/tmp_suning_uos_patched
edac updates for v3.19-rc1
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUhyDVAAoJEAhfPr2O5OEVsdMP/it7jKAKu1uHvVoWfwPcB0nG QZ7Dt3Hu9aZtaZJs9OFOl2RrGyp4tXOK1SM2QInRGRjjquEP83AASk7XJRkXHr61 DTiMxHnKXvGfky4ONS76ZP3JWwfBffT5Y8oXIGiarAyUgcK66mnelrlju0r1XM11 uoUZqOzE5ySfARFcYm9VG53qLG4RxOERqP+EKSyctRE5gCsuymPaSKIwqj7rcg4R QikDJQv2H8y2Ui0T9Dk6urdOjlUpBczGRVaXdY+2FyDfs0KPLEWUQVl8q2Lj/bur 1A10H+p9HdIA9emV2WEetQmJzz7POgn/j+BLkRKImPS5NgKv2Gu5BWiVUKQg4oRt shvcpp38PYSmeDIy16v+3RDf0THSSYxhq7ExlGacIzaRk7G2asgRAWixiVS45NzI yMb17ZJlHhzVMEyoSlTJH90o4y6UT9njZ7TcK3+9wmhbFyIlGWrrD1Mp56PDCYes KO5VRYkwnw8GAd7gH0xwtHRREQYt4VneVyb7Ccw2VxrdIffVp1fDhpxnS+tw+Qri 294+RoJlnrp4JIpXerAJgQIIiMsRhg64EQ3rsT4Skj6Hfq4KExkmdrHE38p+FZLO xHURKAt2jDSuu/DqaWpBclJXE4Q+MhS303pn80x0MHbFmRAYxwmWFjgPwQKrzNU9 x47JgdYNpBoF2+WK6ZGo =CeIU -----END PGP SIGNATURE----- Merge tag 'edac/v3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac Pull edac updates from Mauro Carvalho Chehab: - Broadwell-DE support on sb-edac driver - Some fixes at sb-edac driver * tag 'edac/v3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac: sb_edac: Fix typo computing number of banks sb_edac: Add support for Broadwell-DE processor sb_edac: Fix discovery of top-of-low-memory for Haswell sb_edac: Fix erroneous bytes->gigabytes conversion sb_edac: Fix off-by-one error in number of channels
This commit is contained in:
Linus Torvalds
commit
709d9f09b6
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@ -372,7 +372,7 @@ static int edac_create_csrow_object(struct mem_ctl_info *mci,
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{
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int err, chan;
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if (csrow->nr_channels >= EDAC_NR_CHANNELS)
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if (csrow->nr_channels > EDAC_NR_CHANNELS)
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return -ENODEV;
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csrow->dev.type = &csrow_attr_type;
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@ -135,6 +135,7 @@ static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
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#define TOLM 0x80
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#define TOHM 0x84
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#define HASWELL_TOLM 0xd0
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#define HASWELL_TOHM_0 0xd4
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#define HASWELL_TOHM_1 0xd8
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@ -261,6 +262,7 @@ enum type {
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SANDY_BRIDGE,
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IVY_BRIDGE,
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HASWELL,
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BROADWELL,
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};
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struct sbridge_pvt;
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@ -445,7 +447,7 @@ static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
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* - each SMI channel interfaces with a scalable memory buffer
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* - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
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*/
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#define HASWELL_DDRCRCLKCONTROLS 0xa10
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#define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
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#define HASWELL_HASYSDEFEATURE2 0x84
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
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@ -496,6 +498,46 @@ static const struct pci_id_table pci_dev_descr_haswell_table[] = {
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{0,} /* 0 terminated list. */
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};
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/*
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* Broadwell support
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*
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* DE processor:
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* - 1 IMC
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* - 2 DDR3 channels, 2 DPC per channel
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*/
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
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static const struct pci_id_descr pci_dev_descr_broadwell[] = {
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/* first item must be the HA */
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
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};
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static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
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PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
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{0,} /* 0 terminated list. */
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};
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/*
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* pci_device_id table for which devices we are looking for
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*/
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@ -503,6 +545,7 @@ static const struct pci_device_id sbridge_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
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{0,} /* 0 terminated list. */
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};
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@ -706,8 +749,8 @@ static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
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{
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u32 reg;
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pci_read_config_dword(pvt->info.pci_vtd, TOLM, ®);
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return (GET_BITFIELD(reg, 26, 31) << 26) | 0x1ffffff;
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pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
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return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
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}
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static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
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@ -767,12 +810,22 @@ static int check_if_ecc_is_active(const u8 bus, enum type type)
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struct pci_dev *pdev = NULL;
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u32 mcmtr, id;
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if (type == IVY_BRIDGE)
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switch (type) {
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case IVY_BRIDGE:
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id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
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else if (type == HASWELL)
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break;
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case HASWELL:
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id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
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else
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break;
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case SANDY_BRIDGE:
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id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
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break;
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case BROADWELL:
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id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
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break;
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default:
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return -ENODEV;
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}
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pdev = get_pdev_same_bus(bus, id);
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if (!pdev) {
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@ -800,7 +853,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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enum edac_type mode;
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enum mem_type mtype;
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if (pvt->info.type == HASWELL)
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if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
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pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
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else
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pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
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@ -848,7 +901,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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else
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edac_dbg(0, "Memory is unregistered\n");
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if (mtype == MEM_DDR4 || MEM_RDDR4)
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if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
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banks = 16;
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else
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banks = 8;
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@ -909,7 +962,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
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u32 reg;
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u64 limit, prv = 0;
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u64 tmp_mb;
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u32 mb, kb;
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u32 gb, mb;
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u32 rir_way;
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/*
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@ -919,15 +972,17 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
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pvt->tolm = pvt->info.get_tolm(pvt);
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tmp_mb = (1 + pvt->tolm) >> 20;
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mb = div_u64_rem(tmp_mb, 1000, &kb);
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edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm);
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gb = div_u64_rem(tmp_mb, 1024, &mb);
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edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
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gb, (mb*1000)/1024, (u64)pvt->tolm);
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/* Address range is already 45:25 */
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pvt->tohm = pvt->info.get_tohm(pvt);
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tmp_mb = (1 + pvt->tohm) >> 20;
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mb = div_u64_rem(tmp_mb, 1000, &kb);
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edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm);
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gb = div_u64_rem(tmp_mb, 1024, &mb);
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edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
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gb, (mb*1000)/1024, (u64)pvt->tohm);
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/*
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* Step 2) Get SAD range and SAD Interleave list
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@ -949,11 +1004,11 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
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break;
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tmp_mb = (limit + 1) >> 20;
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mb = div_u64_rem(tmp_mb, 1000, &kb);
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gb = div_u64_rem(tmp_mb, 1024, &mb);
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edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
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n_sads,
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get_dram_attr(reg),
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mb, kb,
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gb, (mb*1000)/1024,
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((u64)tmp_mb) << 20L,
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INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
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reg);
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@ -984,9 +1039,9 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
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break;
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tmp_mb = (limit + 1) >> 20;
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mb = div_u64_rem(tmp_mb, 1000, &kb);
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gb = div_u64_rem(tmp_mb, 1024, &mb);
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edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
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n_tads, mb, kb,
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n_tads, gb, (mb*1000)/1024,
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((u64)tmp_mb) << 20L,
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(u32)TAD_SOCK(reg),
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(u32)TAD_CH(reg),
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@ -1009,10 +1064,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
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tad_ch_nilv_offset[j],
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®);
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tmp_mb = TAD_OFFSET(reg) >> 20;
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mb = div_u64_rem(tmp_mb, 1000, &kb);
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gb = div_u64_rem(tmp_mb, 1024, &mb);
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edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
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i, j,
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mb, kb,
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gb, (mb*1000)/1024,
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((u64)tmp_mb) << 20L,
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reg);
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}
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@ -1034,10 +1089,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
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tmp_mb = pvt->info.rir_limit(reg) >> 20;
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rir_way = 1 << RIR_WAY(reg);
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mb = div_u64_rem(tmp_mb, 1000, &kb);
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gb = div_u64_rem(tmp_mb, 1024, &mb);
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edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
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i, j,
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mb, kb,
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gb, (mb*1000)/1024,
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((u64)tmp_mb) << 20L,
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rir_way,
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reg);
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@ -1048,10 +1103,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
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®);
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tmp_mb = RIR_OFFSET(reg) << 6;
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mb = div_u64_rem(tmp_mb, 1000, &kb);
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gb = div_u64_rem(tmp_mb, 1024, &mb);
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edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
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i, j, k,
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mb, kb,
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gb, (mb*1000)/1024,
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((u64)tmp_mb) << 20L,
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(u32)RIR_RNK_TGT(reg),
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reg);
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|
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@ -1089,7 +1144,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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u8 ch_way, sck_way, pkg, sad_ha = 0;
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u32 tad_offset;
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u32 rir_way;
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u32 mb, kb;
|
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u32 mb, gb;
|
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u64 ch_addr, offset, limit = 0, prv = 0;
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|
||||
|
||||
|
|
@ -1179,7 +1234,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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|||
*socket = sad_interleave[idx];
|
||||
edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
|
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idx, sad_way, *socket);
|
||||
} else if (pvt->info.type == HASWELL) {
|
||||
} else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
|
||||
int bits, a7mode = A7MODE(dram_rule);
|
||||
|
||||
if (a7mode) {
|
||||
|
|
@ -1358,10 +1413,10 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
|||
continue;
|
||||
|
||||
limit = pvt->info.rir_limit(reg);
|
||||
mb = div_u64_rem(limit >> 20, 1000, &kb);
|
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gb = div_u64_rem(limit >> 20, 1024, &mb);
|
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edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
|
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n_rir,
|
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mb, kb,
|
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gb, (mb*1000)/1024,
|
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limit,
|
||||
1 << RIR_WAY(reg));
|
||||
if (ch_addr <= limit)
|
||||
|
|
@ -1828,6 +1883,82 @@ static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
|
||||
struct sbridge_dev *sbridge_dev)
|
||||
{
|
||||
struct sbridge_pvt *pvt = mci->pvt_info;
|
||||
struct pci_dev *pdev;
|
||||
int i;
|
||||
|
||||
/* there's only one device per system; not tied to any bus */
|
||||
if (pvt->info.pci_vtd == NULL)
|
||||
/* result will be checked later */
|
||||
pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
|
||||
NULL);
|
||||
|
||||
for (i = 0; i < sbridge_dev->n_devs; i++) {
|
||||
pdev = sbridge_dev->pdev[i];
|
||||
if (!pdev)
|
||||
continue;
|
||||
|
||||
switch (pdev->device) {
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
|
||||
pvt->pci_sad0 = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
|
||||
pvt->pci_sad1 = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
|
||||
pvt->pci_ha0 = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
|
||||
pvt->pci_ta = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
|
||||
pvt->pci_ras = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
|
||||
pvt->pci_tad[0] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
|
||||
pvt->pci_tad[1] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
|
||||
pvt->pci_tad[2] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
|
||||
pvt->pci_tad[3] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
|
||||
pvt->pci_ddrio = pdev;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
|
||||
sbridge_dev->bus,
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
|
||||
pdev);
|
||||
}
|
||||
|
||||
/* Check if everything were registered */
|
||||
if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
|
||||
!pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
|
||||
goto enodev;
|
||||
|
||||
for (i = 0; i < NUM_CHANNELS; i++) {
|
||||
if (!pvt->pci_tad[i])
|
||||
goto enodev;
|
||||
}
|
||||
return 0;
|
||||
|
||||
enodev:
|
||||
sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
Error check routines
|
||||
****************************************************************************/
|
||||
|
|
@ -2240,6 +2371,25 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
|
|||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
break;
|
||||
case BROADWELL:
|
||||
/* rankcfgr isn't used */
|
||||
pvt->info.get_tolm = haswell_get_tolm;
|
||||
pvt->info.get_tohm = haswell_get_tohm;
|
||||
pvt->info.dram_rule = ibridge_dram_rule;
|
||||
pvt->info.get_memory_type = haswell_get_memory_type;
|
||||
pvt->info.get_node_id = haswell_get_node_id;
|
||||
pvt->info.rir_limit = haswell_rir_limit;
|
||||
pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
|
||||
pvt->info.interleave_list = ibridge_interleave_list;
|
||||
pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
|
||||
pvt->info.interleave_pkg = ibridge_interleave_pkg;
|
||||
mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
|
||||
|
||||
/* Store pci devices at mci for faster access */
|
||||
rc = broadwell_mci_bind_devs(mci, sbridge_dev);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Get dimm basic config and the memory layout */
|
||||
|
|
@ -2305,6 +2455,10 @@ static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
|
||||
type = HASWELL;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
|
||||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
|
||||
type = BROADWELL;
|
||||
break;
|
||||
}
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user