forked from luck/tmp_suning_uos_patched
cxgb4vf: added much cleaner implementation of is_t4()
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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d14807dd8e
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70ee366689
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@ -1204,4 +1204,13 @@
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#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
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#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
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#define A_PL_VF_REV 0x4
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#define A_PL_VF_WHOAMI 0x0
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#define A_PL_VF_REVISION 0x8
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#define S_CHIPID 4
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#define M_CHIPID 0xfU
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#define V_CHIPID(x) ((x) << S_CHIPID)
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#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
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#endif /* __T4_REGS_H */
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@ -344,7 +344,6 @@ struct adapter {
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unsigned long registered_device_map;
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unsigned long open_device_map;
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unsigned long flags;
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enum chip_type chip;
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struct adapter_params params;
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/* queue and interrupt resources */
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@ -1064,7 +1064,7 @@ static inline unsigned int mk_adap_vers(const struct adapter *adapter)
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/*
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* Chip version 4, revision 0x3f (cxgb4vf).
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*/
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return CHELSIO_CHIP_VERSION(adapter->chip) | (0x3f << 10);
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return CHELSIO_CHIP_VERSION(adapter->params.chip) | (0x3f << 10);
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}
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/*
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@ -1551,9 +1551,13 @@ static void cxgb4vf_get_regs(struct net_device *dev,
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reg_block_dump(adapter, regbuf,
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T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_FIRST,
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T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_LAST);
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/* T5 adds new registers in the PL Register map.
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*/
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reg_block_dump(adapter, regbuf,
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T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST,
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T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_LAST);
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T4VF_PL_BASE_ADDR + (is_t4(adapter->params.chip)
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? A_PL_VF_WHOAMI : A_PL_VF_REVISION));
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reg_block_dump(adapter, regbuf,
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T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST,
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T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST);
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@ -2087,6 +2091,7 @@ static int adap_init0(struct adapter *adapter)
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unsigned int ethqsets;
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int err;
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u32 param, val = 0;
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unsigned int chipid;
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/*
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* Wait for the device to become ready before proceeding ...
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@ -2114,12 +2119,14 @@ static int adap_init0(struct adapter *adapter)
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return err;
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}
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adapter->params.chip = 0;
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switch (adapter->pdev->device >> 12) {
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case CHELSIO_T4:
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adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
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adapter->params.chip = CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
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break;
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case CHELSIO_T5:
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adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T5, 0);
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chipid = G_REV(t4_read_reg(adapter, A_PL_VF_REV));
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adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
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break;
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}
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@ -537,7 +537,7 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
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*/
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if (fl->pend_cred >= FL_PER_EQ_UNIT) {
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val = PIDX(fl->pend_cred / FL_PER_EQ_UNIT);
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if (!is_t4(adapter->chip))
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if (!is_t4(adapter->params.chip))
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val |= DBTYPE(1);
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wmb();
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t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
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@ -39,21 +39,28 @@
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#include "../cxgb4/t4fw_api.h"
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#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
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#define CHELSIO_CHIP_VERSION(code) ((code) >> 4)
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#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
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#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
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/* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
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*
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* V = "4" for T4; "5" for T5, etc. or
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* = "a" for T4 FPGA; "b" for T4 FPGA, etc.
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* F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
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* PP = adapter product designation
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*/
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#define CHELSIO_T4 0x4
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#define CHELSIO_T5 0x5
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enum chip_type {
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T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0),
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T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
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T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
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T4_FIRST_REV = T4_A1,
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T4_LAST_REV = T4_A3,
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T4_LAST_REV = T4_A2,
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T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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T5_FIRST_REV = T5_A1,
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T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
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T5_FIRST_REV = T5_A0,
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T5_LAST_REV = T5_A1,
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};
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@ -203,6 +210,7 @@ struct adapter_params {
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struct vpd_params vpd; /* Vital Product Data */
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struct rss_params rss; /* Receive Side Scaling */
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struct vf_resources vfres; /* Virtual Function Resource limits */
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enum chip_type chip; /* chip code */
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u8 nports; /* # of Ethernet "ports" */
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};
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@ -253,7 +261,7 @@ static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
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static inline int is_t4(enum chip_type chip)
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{
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return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV);
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return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
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}
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int t4vf_wait_dev_ready(struct adapter *);
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@ -1027,7 +1027,7 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
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unsigned nfilters = 0;
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unsigned int rem = naddr;
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struct fw_vi_mac_cmd cmd, rpl;
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unsigned int max_naddr = is_t4(adapter->chip) ?
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unsigned int max_naddr = is_t4(adapter->params.chip) ?
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NUM_MPS_CLS_SRAM_L_INSTANCES :
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NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
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@ -1121,7 +1121,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
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struct fw_vi_mac_exact *p = &cmd.u.exact[0];
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size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
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u.exact[1]), 16);
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unsigned int max_naddr = is_t4(adapter->chip) ?
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unsigned int max_naddr = is_t4(adapter->params.chip) ?
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NUM_MPS_CLS_SRAM_L_INSTANCES :
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NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
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