forked from luck/tmp_suning_uos_patched
Merge branch 'remotes/lorenzo/pci/cadence'
- Deprecate 'cdns,max-outbound-regions' and 'cdns,no-bar-match-nbits' bindings in favor of deriving them from 'ranges' and 'dma-ranges' (Kishon Vijay Abraham I) - Read Vendor and Device ID as 32 bits (not 16) from DT (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DT PCI: cadence: Remove "cdns,max-outbound-regions" DT property dt-bindings: PCI: cadence: Deprecate inbound/outbound specific bindings
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commit
712879510f
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@ -10,7 +10,7 @@ maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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allOf:
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- $ref: "cdns-pcie.yaml#"
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- $ref: "cdns-pcie-ep.yaml#"
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- $ref: "pci-ep.yaml#"
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properties:
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@ -45,8 +45,6 @@ examples:
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#size-cells = <2>;
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bus-range = <0x0 0xff>;
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linux,pci-domain = <0>;
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cdns,max-outbound-regions = <16>;
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cdns,no-bar-match-nbits = <32>;
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vendor-id = <0x17cd>;
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device-id = <0x0200>;
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@ -57,6 +55,7 @@ examples:
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ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
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<0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
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dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
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#interrupt-cells = <0x1>;
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25
Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
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25
Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
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@ -0,0 +1,25 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Cadence PCIe Device
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maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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allOf:
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- $ref: "cdns-pcie.yaml#"
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properties:
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cdns,max-outbound-regions:
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description: maximum number of outbound regions
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 32
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default: 32
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required:
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- cdns,max-outbound-regions
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@ -14,6 +14,15 @@ allOf:
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- $ref: "cdns-pcie.yaml#"
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properties:
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cdns,max-outbound-regions:
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description: maximum number of outbound regions
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 32
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default: 32
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deprecated: true
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cdns,no-bar-match-nbits:
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description:
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Set into the no BAR match register to configure the number of least
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@ -23,5 +32,6 @@ properties:
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minimum: 0
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maximum: 64
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default: 32
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deprecated: true
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msi-parent: true
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@ -10,14 +10,6 @@ maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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properties:
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cdns,max-outbound-regions:
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description: maximum number of outbound regions
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 32
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default: 32
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phys:
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description:
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One per lane if more than one in the list. If only one PHY listed it must
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@ -140,9 +140,6 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
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for_each_of_pci_range(&parser, &range) {
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bool is_io;
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if (r >= rc->max_regions)
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break;
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if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
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is_io = false;
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else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
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@ -219,17 +216,14 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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pcie = &rc->pcie;
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pcie->is_rc = true;
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rc->max_regions = 32;
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of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
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rc->no_bar_nbits = 32;
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of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
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rc->vendor_id = 0xffff;
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of_property_read_u16(np, "vendor-id", &rc->vendor_id);
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of_property_read_u32(np, "vendor-id", &rc->vendor_id);
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rc->device_id = 0xffff;
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of_property_read_u16(np, "device-id", &rc->device_id);
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of_property_read_u32(np, "device-id", &rc->device_id);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
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pcie->reg_base = devm_ioremap_resource(dev, res);
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@ -251,7 +251,6 @@ struct cdns_pcie {
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* @bus_range: first/last buses behind the PCIe host controller
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* @cfg_base: IO mapped window to access the PCI configuration space of a
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* single function at a time
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* @max_regions: maximum number of regions supported by the hardware
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* @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
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* translation (nbits sets into the "no BAR match" register)
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* @vendor_id: PCI vendor ID
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@ -262,10 +261,9 @@ struct cdns_pcie_rc {
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struct resource *cfg_res;
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struct resource *bus_range;
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void __iomem *cfg_base;
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u32 max_regions;
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u32 no_bar_nbits;
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u16 vendor_id;
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u16 device_id;
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u32 vendor_id;
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u32 device_id;
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};
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/**
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