forked from luck/tmp_suning_uos_patched
Documentation: remove old sbc8260 board specific information
This file contains 8 yr. old board specific information that was for the now gone ppc implementation, and it pre-dates widespread u-boot support. Any of the technical details of the board memory map would be more appropriately captured in a dts if I revive it as powerpc anyway. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Paul Gortmaker
Kumar Gala
parent
dddb8d3111
commit
74deace2f9
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@ -20,8 +20,6 @@ mpc52xx-device-tree-bindings.txt
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- MPC5200 Device Tree Bindings
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ppc_htab.txt
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- info about the Linux/PPC /proc/ppc_htab entry
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SBC8260_memory_mapping.txt
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- EST SBC8260 board info
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smp.txt
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- use and state info about Linux/PPC on MP machines
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sound.txt
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@ -1,197 +0,0 @@
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Please mail me (Jon Diekema, diekema_jon@si.com or diekema@cideas.com)
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if you have questions, comments or corrections.
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* EST SBC8260 Linux memory mapping rules
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http://www.estc.com/
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http://www.estc.com/products/boards/SBC8260-8240_ds.html
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Initial conditions:
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-------------------
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Tasks that need to be perform by the boot ROM before control is
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transferred to zImage (compressed Linux kernel):
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- Define the IMMR to 0xf0000000
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- Initialize the memory controller so that RAM is available at
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physical address 0x00000000. On the SBC8260 is this 16M (64M)
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SDRAM.
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- The boot ROM should only clear the RAM that it is using.
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The reason for doing this is to enhances the chances of a
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successful post mortem on a Linux panic. One of the first
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items to examine is the 16k (LOG_BUF_LEN) circular console
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buffer called log_buf which is defined in kernel/printk.c.
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- To enhance boot ROM performance, the I-cache can be enabled.
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Date: Mon, 22 May 2000 14:21:10 -0700
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From: Neil Russell <caret@c-side.com>
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LiMon (LInux MONitor) runs with and starts Linux with MMU
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off, I-cache enabled, D-cache disabled. The I-cache doesn't
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need hints from the MMU to work correctly as the D-cache
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does. No D-cache means no special code to handle devices in
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the presence of cache (no snooping, etc). The use of the
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I-cache means that the monitor can run acceptably fast
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directly from ROM, rather than having to copy it to RAM.
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- Build the board information structure (see
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include/asm-ppc/est8260.h for its definition)
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- The compressed Linux kernel (zImage) contains a bootstrap loader
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that is position independent; you can load it into any RAM,
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ROM or FLASH memory address >= 0x00500000 (above 5 MB), or
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at its link address of 0x00400000 (4 MB).
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Note: If zImage is loaded at its link address of 0x00400000 (4 MB),
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then zImage will skip the step of moving itself to
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its link address.
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- Load R3 with the address of the board information structure
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- Transfer control to zImage
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- The Linux console port is SMC1, and the baud rate is controlled
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from the bi_baudrate field of the board information structure.
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On thing to keep in mind when picking the baud rate, is that
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there is no flow control on the SMC ports. I would stick
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with something safe and standard like 19200.
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On the EST SBC8260, the SMC1 port is on the COM1 connector of
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the board.
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EST SBC8260 defaults:
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---------------------
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Chip
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Memory Sel Bus Use
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--------------------- --- --- ----------------------------------
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0x00000000-0x03FFFFFF CS2 60x (16M or 64M)/64M SDRAM
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0x04000000-0x04FFFFFF CS4 local 4M/16M SDRAM (soldered to the board)
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0x21000000-0x21000000 CS7 60x 1B/64K Flash present detect (from the flash SIMM)
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0x21000001-0x21000001 CS7 60x 1B/64K Switches (read) and LEDs (write)
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0x22000000-0x2200FFFF CS5 60x 8K/64K EEPROM
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0xFC000000-0xFCFFFFFF CS6 60x 2M/16M flash (8 bits wide, soldered to the board)
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0xFE000000-0xFFFFFFFF CS0 60x 4M/16M flash (SIMM)
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Notes:
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------
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- The chip selects can map 32K blocks and up (powers of 2)
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- The SDRAM machine can handled up to 128Mbytes per chip select
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- Linux uses the 60x bus memory (the SDRAM DIMM) for the
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communications buffers.
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- BATs can map 128K-256Mbytes each. There are four data BATs and
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four instruction BATs. Generally the data and instruction BATs
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are mapped the same.
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- The IMMR must be set above the kernel virtual memory addresses,
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which start at 0xC0000000. Otherwise, the kernel may crash as
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soon as you start any threads or processes due to VM collisions
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in the kernel or user process space.
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Details from Dan Malek <dan_malek@mvista.com> on 10/29/1999:
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The user application virtual space consumes the first 2 Gbytes
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(0x00000000 to 0x7FFFFFFF). The kernel virtual text starts at
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0xC0000000, with data following. There is a "protection hole"
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between the end of kernel data and the start of the kernel
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dynamically allocated space, but this space is still within
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0xCxxxxxxx.
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Obviously the kernel can't map any physical addresses 1:1 in
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these ranges.
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Details from Dan Malek <dan_malek@mvista.com> on 5/19/2000:
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During the early kernel initialization, the kernel virtual
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memory allocator is not operational. Prior to this KVM
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initialization, we choose to map virtual to physical addresses
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1:1. That is, the kernel virtual address exactly matches the
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physical address on the bus. These mappings are typically done
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in arch/ppc/kernel/head.S, or arch/ppc/mm/init.c. Only
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absolutely necessary mappings should be done at this time, for
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example board control registers or a serial uart. Normal device
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driver initialization should map resources later when necessary.
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Although platform dependent, and certainly the case for embedded
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8xx, traditionally memory is mapped at physical address zero,
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and I/O devices above physical address 0x80000000. The lowest
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and highest (above 0xf0000000) I/O addresses are traditionally
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used for devices or registers we need to map during kernel
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initialization and prior to KVM operation. For this reason,
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and since it followed prior PowerPC platform examples, I chose
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to map the embedded 8xx kernel to the 0xc0000000 virtual address.
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This way, we can enable the MMU to map the kernel for proper
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operation, and still map a few windows before the KVM is operational.
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On some systems, you could possibly run the kernel at the
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0x80000000 or any other virtual address. It just depends upon
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mapping that must be done prior to KVM operational. You can never
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map devices or kernel spaces that overlap with the user virtual
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space. This is why default IMMR mapping used by most BDM tools
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won't work. They put the IMMR at something like 0x10000000 or
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0x02000000 for example. You simply can't map these addresses early
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in the kernel, and continue proper system operation.
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The embedded 8xx/82xx kernel is mature enough that all you should
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need to do is map the IMMR someplace at or above 0xf0000000 and it
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should boot far enough to get serial console messages and KGDB
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connected on any platform. There are lots of other subtle memory
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management design features that you simply don't need to worry
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about. If you are changing functions related to MMU initialization,
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you are likely breaking things that are known to work and are
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heading down a path of disaster and frustration. Your changes
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should be to make the flexibility of the processor fit Linux,
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not force arbitrary and non-workable memory mappings into Linux.
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- You don't want to change KERNELLOAD or KERNELBASE, otherwise the
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virtual memory and MMU code will get confused.
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arch/ppc/Makefile:KERNELLOAD = 0xc0000000
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include/asm-ppc/page.h:#define PAGE_OFFSET 0xc0000000
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include/asm-ppc/page.h:#define KERNELBASE PAGE_OFFSET
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- RAM is at physical address 0x00000000, and gets mapped to
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virtual address 0xC0000000 for the kernel.
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Physical addresses used by the Linux kernel:
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--------------------------------------------
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0x00000000-0x3FFFFFFF 1GB reserved for RAM
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0xF0000000-0xF001FFFF 128K IMMR 64K used for dual port memory,
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64K for 8260 registers
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Logical addresses used by the Linux kernel:
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-------------------------------------------
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0xF0000000-0xFFFFFFFF 256M BAT0 (IMMR: dual port RAM, registers)
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0xE0000000-0xEFFFFFFF 256M BAT1 (I/O space for custom boards)
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0xC0000000-0xCFFFFFFF 256M BAT2 (RAM)
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0xD0000000-0xDFFFFFFF 256M BAT3 (if RAM > 256MByte)
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EST SBC8260 Linux mapping:
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--------------------------
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DBAT0, IBAT0, cache inhibited:
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Chip
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Memory Sel Use
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--------------------- --- ---------------------------------
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0xF0000000-0xF001FFFF n/a IMMR: dual port RAM, registers
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DBAT1, IBAT1, cache inhibited:
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