forked from luck/tmp_suning_uos_patched
dt-bindings: firmware: imx: Move system control into dt-binding headfile
i.MX8 SoCs DTS file needs system control macro definitions, so move them into dt-binding headfile, then include/linux/firmware/imx/types.h can be removed and those drivers using it should be changed accordingly. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -8,7 +8,6 @@
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*/
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#include <linux/err.h>
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#include <linux/firmware/imx/types.h>
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#include <linux/firmware/imx/ipc.h>
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#include <linux/firmware/imx/sci.h>
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#include <linux/interrupt.h>
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@ -3,9 +3,9 @@
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* Copyright 2018-2020 NXP.
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <linux/err.h>
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#include <linux/firmware/imx/sci.h>
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#include <linux/firmware/imx/types.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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@ -547,4 +547,55 @@
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#define IMX_SC_R_ATTESTATION 545
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#define IMX_SC_R_LAST 546
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/*
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* Defines for SC CONTROL
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*/
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#define IMX_SC_C_TEMP 0
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#define IMX_SC_C_TEMP_HI 1
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#define IMX_SC_C_TEMP_LOW 2
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#define IMX_SC_C_PXL_LINK_MST1_ADDR 3
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#define IMX_SC_C_PXL_LINK_MST2_ADDR 4
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#define IMX_SC_C_PXL_LINK_MST_ENB 5
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#define IMX_SC_C_PXL_LINK_MST1_ENB 6
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#define IMX_SC_C_PXL_LINK_MST2_ENB 7
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#define IMX_SC_C_PXL_LINK_SLV1_ADDR 8
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#define IMX_SC_C_PXL_LINK_SLV2_ADDR 9
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#define IMX_SC_C_PXL_LINK_MST_VLD 10
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#define IMX_SC_C_PXL_LINK_MST1_VLD 11
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#define IMX_SC_C_PXL_LINK_MST2_VLD 12
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#define IMX_SC_C_SINGLE_MODE 13
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#define IMX_SC_C_ID 14
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#define IMX_SC_C_PXL_CLK_POLARITY 15
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#define IMX_SC_C_LINESTATE 16
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#define IMX_SC_C_PCIE_G_RST 17
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#define IMX_SC_C_PCIE_BUTTON_RST 18
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#define IMX_SC_C_PCIE_PERST 19
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#define IMX_SC_C_PHY_RESET 20
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#define IMX_SC_C_PXL_LINK_RATE_CORRECTION 21
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#define IMX_SC_C_PANIC 22
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#define IMX_SC_C_PRIORITY_GROUP 23
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#define IMX_SC_C_TXCLK 24
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#define IMX_SC_C_CLKDIV 25
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#define IMX_SC_C_DISABLE_50 26
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#define IMX_SC_C_DISABLE_125 27
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#define IMX_SC_C_SEL_125 28
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#define IMX_SC_C_MODE 29
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#define IMX_SC_C_SYNC_CTRL0 30
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#define IMX_SC_C_KACHUNK_CNT 31
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#define IMX_SC_C_KACHUNK_SEL 32
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#define IMX_SC_C_SYNC_CTRL1 33
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#define IMX_SC_C_DPI_RESET 34
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#define IMX_SC_C_MIPI_RESET 35
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#define IMX_SC_C_DUAL_MODE 36
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#define IMX_SC_C_VOLTAGE 37
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#define IMX_SC_C_PXL_LINK_SEL 38
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#define IMX_SC_C_OFS_SEL 39
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#define IMX_SC_C_OFS_AUDIO 40
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#define IMX_SC_C_OFS_PERIPH 41
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#define IMX_SC_C_OFS_IRQ 42
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#define IMX_SC_C_RST0 43
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#define IMX_SC_C_RST1 44
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#define IMX_SC_C_SEL0 45
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#define IMX_SC_C_LAST 46
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#endif /* __DT_BINDINGS_RSCRC_IMX_H */
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@ -11,7 +11,6 @@
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#define _SC_SCI_H
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#include <linux/firmware/imx/ipc.h>
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#include <linux/firmware/imx/types.h>
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#include <linux/firmware/imx/svc/misc.h>
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#include <linux/firmware/imx/svc/pm.h>
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@ -1,65 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017~2018 NXP
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*
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* Header file containing types used across multiple service APIs.
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*/
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#ifndef _SC_TYPES_H
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#define _SC_TYPES_H
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/*
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* This type is used to indicate a control.
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*/
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enum imx_sc_ctrl {
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IMX_SC_C_TEMP = 0,
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IMX_SC_C_TEMP_HI = 1,
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IMX_SC_C_TEMP_LOW = 2,
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IMX_SC_C_PXL_LINK_MST1_ADDR = 3,
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IMX_SC_C_PXL_LINK_MST2_ADDR = 4,
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IMX_SC_C_PXL_LINK_MST_ENB = 5,
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IMX_SC_C_PXL_LINK_MST1_ENB = 6,
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IMX_SC_C_PXL_LINK_MST2_ENB = 7,
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IMX_SC_C_PXL_LINK_SLV1_ADDR = 8,
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IMX_SC_C_PXL_LINK_SLV2_ADDR = 9,
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IMX_SC_C_PXL_LINK_MST_VLD = 10,
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IMX_SC_C_PXL_LINK_MST1_VLD = 11,
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IMX_SC_C_PXL_LINK_MST2_VLD = 12,
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IMX_SC_C_SINGLE_MODE = 13,
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IMX_SC_C_ID = 14,
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IMX_SC_C_PXL_CLK_POLARITY = 15,
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IMX_SC_C_LINESTATE = 16,
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IMX_SC_C_PCIE_G_RST = 17,
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IMX_SC_C_PCIE_BUTTON_RST = 18,
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IMX_SC_C_PCIE_PERST = 19,
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IMX_SC_C_PHY_RESET = 20,
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IMX_SC_C_PXL_LINK_RATE_CORRECTION = 21,
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IMX_SC_C_PANIC = 22,
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IMX_SC_C_PRIORITY_GROUP = 23,
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IMX_SC_C_TXCLK = 24,
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IMX_SC_C_CLKDIV = 25,
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IMX_SC_C_DISABLE_50 = 26,
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IMX_SC_C_DISABLE_125 = 27,
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IMX_SC_C_SEL_125 = 28,
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IMX_SC_C_MODE = 29,
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IMX_SC_C_SYNC_CTRL0 = 30,
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IMX_SC_C_KACHUNK_CNT = 31,
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IMX_SC_C_KACHUNK_SEL = 32,
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IMX_SC_C_SYNC_CTRL1 = 33,
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IMX_SC_C_DPI_RESET = 34,
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IMX_SC_C_MIPI_RESET = 35,
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IMX_SC_C_DUAL_MODE = 36,
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IMX_SC_C_VOLTAGE = 37,
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IMX_SC_C_PXL_LINK_SEL = 38,
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IMX_SC_C_OFS_SEL = 39,
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IMX_SC_C_OFS_AUDIO = 40,
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IMX_SC_C_OFS_PERIPH = 41,
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IMX_SC_C_OFS_IRQ = 42,
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IMX_SC_C_RST0 = 43,
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IMX_SC_C_RST1 = 44,
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IMX_SC_C_SEL0 = 45,
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IMX_SC_C_LAST
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};
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#endif /* _SC_TYPES_H */
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