forked from luck/tmp_suning_uos_patched
drm/radeon: Modify radeon_pm_in_vbl to use radeon_get_crtc_scanoutpos()
radeon_pm_in_vbl() didn't report in vblank status accurately. Make it a wrapper around radeon_get_crtc_scanoutpos() which corrects for biases, so it reports accurately. radeon_pm_in_vbl() will only report in_vbl if all active crtc's are currently inside vblank. agd5f: use rdev->num_crtc rather than hardcoding the crtc count Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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6383cf7d78
commit
75fa0b08e5
@ -712,73 +712,21 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
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static bool radeon_pm_in_vbl(struct radeon_device *rdev)
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{
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u32 stat_crtc = 0, vbl = 0, position = 0;
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int crtc, vpos, hpos, vbl_status;
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bool in_vbl = true;
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if (ASIC_IS_DCE4(rdev)) {
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if (rdev->pm.active_crtcs & (1 << 0)) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
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}
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if (rdev->pm.active_crtcs & (1 << 1)) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
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}
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if (rdev->pm.active_crtcs & (1 << 2)) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
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}
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if (rdev->pm.active_crtcs & (1 << 3)) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
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}
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if (rdev->pm.active_crtcs & (1 << 4)) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
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}
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if (rdev->pm.active_crtcs & (1 << 5)) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
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}
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} else if (ASIC_IS_AVIVO(rdev)) {
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if (rdev->pm.active_crtcs & (1 << 0)) {
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vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
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position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
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}
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if (rdev->pm.active_crtcs & (1 << 1)) {
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vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
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position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
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}
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if (position < vbl && position > 1)
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in_vbl = false;
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} else {
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if (rdev->pm.active_crtcs & (1 << 0)) {
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stat_crtc = RREG32(RADEON_CRTC_STATUS);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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if (rdev->pm.active_crtcs & (1 << 1)) {
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stat_crtc = RREG32(RADEON_CRTC2_STATUS);
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if (!(stat_crtc & 1))
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/* Iterate over all active crtc's. All crtc's must be in vblank,
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* otherwise return in_vbl == false.
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*/
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for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
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if (rdev->pm.active_crtcs & (1 << crtc)) {
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vbl_status = radeon_get_crtc_scanoutpos(rdev, crtc, &vpos, &hpos);
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if ((vbl_status & RADEON_SCANOUTPOS_VALID) &&
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!(vbl_status & RADEON_SCANOUTPOS_INVBL))
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in_vbl = false;
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}
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}
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if (position < vbl && position > 1)
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in_vbl = false;
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return in_vbl;
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}
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