forked from luck/tmp_suning_uos_patched
drm fixes for 5.4-rc2
core: - writeback fixes i915: - Fix DP-MST crtc_mask - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. komeda: - memory leak fix tilcdc: - include fix amdgpu: - Enable bulk moves - Power metrics fixes for Navi - Fix S4 regression - Add query for tcc disabled mask - Fix several leaks in error paths - randconfig fixes - clang fixes -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdlvpMAAoJEAx081l5xIa+yowP/2m/4P0V7u/BOopf83h6O2OD iWf6IbnPA6UdZbGiwyTu1814hhc1ijDKBcj005YLK7CXhangzhTYUBdYDKJTjJzP OYnDWV+CP03qX87CHozb7dHqdAtosdaXnXNipUkLFRM9fx8Q6yA4ERyt7NB25qn+ c3GIaC7uU6yN9nn/FLaAc94FCn8Jy0HY6Fm/VIbugRulVeRp2Gq9jV+BIXoxTCxE OBhxQnSS25VCoo/lyUGVEZ+LFtfaiRJVO+MMhYKdNNAgxXnGqkxVk8jfxnK4MRBP lhbSL1WC0T2B5+ahT4bwKu9eluW2DONfkiQ5HzQKUepcmHKNgIWjOKcf9lxSZ0yz ITzh4qyjF7+qjtSKXFPSYGQuBnLrU2wY4euMa1S7qQAq0fLXia5IJL63jNqc5iSG e5vziPeP1iwouDIvekE4PDpUt58VyFIiD4z0jTNJPwN3w0OqKfqAWsFZdTHIIKwy 2qQhEv+RnVwCKN0uT+9YgkKKvAOmeBJ5MZHueQv9PJfVRndk8Zqzog38whsgSebZ Z5i3AO7SPzPusEULkSc/gR5EyLHiklUXS6DaTuJCZ80DVlNs5+QPCcFAnKAPh0kj isyt2/l9rEZucRiPe1t9OMQ+zVmfCnxZIMtxo5K0TmHon1Rrc11XOI4wtOzsyDmo eEvWg+JWqlm57TS1jzqq =2MxC -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2019-10-04' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Been offline for 3 days, got back and had some fixes queued up. Nothing too major, the i915 dp-mst fix is important, and amdgpu has a bulk move speedup fix and some regressions, but nothing too insane for an rc2 pull. The intel fixes are also 2 weeks worth, they missed the boat last week. core: - writeback fixes i915: - Fix DP-MST crtc_mask - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. komeda: - memory leak fix tilcdc: - include fix amdgpu: - Enable bulk moves - Power metrics fixes for Navi - Fix S4 regression - Add query for tcc disabled mask - Fix several leaks in error paths - randconfig fixes - clang fixes" * tag 'drm-fixes-2019-10-04' of git://anongit.freedesktop.org/drm/drm: (21 commits) Revert "drm/i915: Fix DP-MST crtc_mask" drm/omap: fix max fclk divider for omap36xx drm/i915: Fix g4x sprite scaling stride check with GTT remapping drm/i915/dp: Fix dsc bpp calculations, v5. drm/amd/display: fix dcn21 Makefile for clang drm/amd/display: hide an unused variable drm/amdgpu: display_mode_vba_21: remove uint typedef drm/amdgpu: hide another #warning drm/amdgpu: make pmu support optional, again drm/amd/display: memory leak drm/amdgpu: fix multiple memory leaks in acp_hw_init drm/amdgpu: return tcc_disabled_mask to userspace drm/amdgpu: don't increment vram lost if we are in hibernation Revert "drm/amdgpu: disable stutter mode for renoir" drm/amd/powerplay: add sensor lock support for smu drm/amd/powerplay: change metrics update period from 1ms to 100ms drm/amdgpu: revert "disable bulk moves for now" drm/tilcdc: include linux/pinctrl/consumer.h again drm/komeda: prevent memory leak in komeda_wb_connector_add drm: Clear the fence pointer when writeback job signaled ...
This commit is contained in:
commit
768b47b7a9
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@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
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amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
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amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
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amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
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amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o
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amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o
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amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
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@ -189,7 +189,7 @@ static int acp_hw_init(void *handle)
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u32 val = 0;
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u32 count = 0;
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struct device *dev;
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struct i2s_platform_data *i2s_pdata;
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struct i2s_platform_data *i2s_pdata = NULL;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -231,20 +231,21 @@ static int acp_hw_init(void *handle)
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adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
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GFP_KERNEL);
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if (adev->acp.acp_cell == NULL)
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return -ENOMEM;
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if (adev->acp.acp_cell == NULL) {
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r = -ENOMEM;
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goto failure;
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}
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adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
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if (adev->acp.acp_res == NULL) {
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kfree(adev->acp.acp_cell);
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return -ENOMEM;
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r = -ENOMEM;
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goto failure;
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}
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i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
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if (i2s_pdata == NULL) {
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kfree(adev->acp.acp_res);
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kfree(adev->acp.acp_cell);
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return -ENOMEM;
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r = -ENOMEM;
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goto failure;
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}
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switch (adev->asic_type) {
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@ -341,14 +342,14 @@ static int acp_hw_init(void *handle)
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r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
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ACP_DEVS);
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if (r)
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return r;
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goto failure;
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for (i = 0; i < ACP_DEVS ; i++) {
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dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
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r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
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if (r) {
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dev_err(dev, "Failed to add dev to genpd\n");
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return r;
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goto failure;
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}
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}
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@ -367,7 +368,8 @@ static int acp_hw_init(void *handle)
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break;
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if (--count == 0) {
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dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
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return -ETIMEDOUT;
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r = -ETIMEDOUT;
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goto failure;
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}
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udelay(100);
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}
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@ -384,7 +386,8 @@ static int acp_hw_init(void *handle)
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break;
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if (--count == 0) {
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dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
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return -ETIMEDOUT;
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r = -ETIMEDOUT;
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goto failure;
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}
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udelay(100);
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}
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@ -393,6 +396,13 @@ static int acp_hw_init(void *handle)
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val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
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cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
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return 0;
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failure:
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kfree(i2s_pdata);
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kfree(adev->acp.acp_res);
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kfree(adev->acp.acp_cell);
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kfree(adev->acp.acp_genpd);
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return r;
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}
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/**
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|
|
|
@ -81,9 +81,10 @@
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* - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
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* - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
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* - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
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* - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
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*/
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#define KMS_DRIVER_MAJOR 3
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#define KMS_DRIVER_MINOR 34
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#define KMS_DRIVER_MINOR 35
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#define KMS_DRIVER_PATCHLEVEL 0
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#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
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|
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|
@ -165,6 +165,7 @@ struct amdgpu_gfx_config {
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uint32_t num_sc_per_sh;
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uint32_t num_packer_per_sc;
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uint32_t pa_sc_tile_steering_override;
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uint64_t tcc_disabled_mask;
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};
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struct amdgpu_cu_info {
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|
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@ -787,6 +787,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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dev_info.pa_sc_tile_steering_override =
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adev->gfx.config.pa_sc_tile_steering_override;
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dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
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return copy_to_user(out, &dev_info,
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min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
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}
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@ -603,14 +603,12 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
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struct ttm_bo_global *glob = adev->mman.bdev.glob;
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struct amdgpu_vm_bo_base *bo_base;
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#if 0
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if (vm->bulk_moveable) {
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spin_lock(&glob->lru_lock);
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ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
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spin_unlock(&glob->lru_lock);
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return;
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}
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#endif
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memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
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@ -1691,6 +1691,17 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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}
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}
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static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
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{
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/* TCCs are global (not instanced). */
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uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
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adev->gfx.config.tcc_disabled_mask =
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REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
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(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
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}
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static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
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{
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u32 tmp;
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@ -1702,6 +1713,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
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gfx_v10_0_setup_rb(adev);
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gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
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gfx_v10_0_get_tcc_info(adev);
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adev->gfx.config.pa_sc_tile_steering_override =
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gfx_v10_0_init_pa_sc_tile_steering_override(adev);
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|
|
|
@ -317,10 +317,12 @@ static int nv_asic_reset(struct amdgpu_device *adev)
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struct smu_context *smu = &adev->smu;
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if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
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amdgpu_inc_vram_lost(adev);
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if (!adev->in_suspend)
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amdgpu_inc_vram_lost(adev);
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ret = smu_baco_reset(smu);
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} else {
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amdgpu_inc_vram_lost(adev);
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if (!adev->in_suspend)
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amdgpu_inc_vram_lost(adev);
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ret = nv_asic_mode1_reset(adev);
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}
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|
|
|
@ -558,12 +558,14 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
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{
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switch (soc15_asic_reset_method(adev)) {
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case AMD_RESET_METHOD_BACO:
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amdgpu_inc_vram_lost(adev);
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if (!adev->in_suspend)
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amdgpu_inc_vram_lost(adev);
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return soc15_asic_baco_reset(adev);
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case AMD_RESET_METHOD_MODE2:
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return soc15_mode2_reset(adev);
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default:
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amdgpu_inc_vram_lost(adev);
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if (!adev->in_suspend)
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amdgpu_inc_vram_lost(adev);
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return soc15_asic_mode1_reset(adev);
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}
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}
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|
@ -771,8 +773,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#else
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# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
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#endif
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amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
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break;
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|
|
|
@ -2385,8 +2385,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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|||
|
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if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
|
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dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
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if (adev->asic_type == CHIP_RENOIR)
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dm->dc->debug.disable_stutter = true;
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|
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return 0;
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fail:
|
||||
|
@ -6019,7 +6017,9 @@ static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
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struct drm_crtc *crtc;
|
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struct drm_crtc_state *old_crtc_state, *new_crtc_state;
|
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int i;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
enum amdgpu_dm_pipe_crc_source source;
|
||||
#endif
|
||||
|
||||
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
|
||||
new_crtc_state, i) {
|
||||
|
|
|
@ -668,6 +668,7 @@ struct clock_source *dce100_clock_source_create(
|
|||
return &clk_src->base;
|
||||
}
|
||||
|
||||
kfree(clk_src);
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -714,6 +714,7 @@ struct clock_source *dce110_clock_source_create(
|
|||
return &clk_src->base;
|
||||
}
|
||||
|
||||
kfree(clk_src);
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -687,6 +687,7 @@ struct clock_source *dce112_clock_source_create(
|
|||
return &clk_src->base;
|
||||
}
|
||||
|
||||
kfree(clk_src);
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -500,6 +500,7 @@ static struct clock_source *dce120_clock_source_create(
|
|||
return &clk_src->base;
|
||||
}
|
||||
|
||||
kfree(clk_src);
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -701,6 +701,7 @@ struct clock_source *dce80_clock_source_create(
|
|||
return &clk_src->base;
|
||||
}
|
||||
|
||||
kfree(clk_src);
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -786,6 +786,7 @@ struct clock_source *dcn10_clock_source_create(
|
|||
return &clk_src->base;
|
||||
}
|
||||
|
||||
kfree(clk_src);
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -1077,6 +1077,7 @@ struct clock_source *dcn20_clock_source_create(
|
|||
return &clk_src->base;
|
||||
}
|
||||
|
||||
kfree(clk_src);
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -3,7 +3,17 @@
|
|||
|
||||
DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
|
||||
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
|
||||
ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
|
||||
cc_stack_align := -mpreferred-stack-boundary=4
|
||||
else ifneq ($(call cc-option, -mstack-alignment=16),)
|
||||
cc_stack_align := -mstack-alignment=16
|
||||
endif
|
||||
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse $(cc_stack_align)
|
||||
|
||||
ifdef CONFIG_CC_IS_CLANG
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2
|
||||
endif
|
||||
|
||||
AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
|
||||
|
||||
|
|
|
@ -39,9 +39,6 @@
|
|||
* ways. Unless there is something clearly wrong with it the code should
|
||||
* remain as-is as it provides us with a guarantee from HW that it is correct.
|
||||
*/
|
||||
|
||||
typedef unsigned int uint;
|
||||
|
||||
typedef struct {
|
||||
double DPPCLK;
|
||||
double DISPCLK;
|
||||
|
@ -4774,7 +4771,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0;
|
||||
mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
|
||||
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
|
||||
uint m;
|
||||
unsigned int m;
|
||||
|
||||
locals->cursor_bw[k] = 0;
|
||||
locals->cursor_bw_pre[k] = 0;
|
||||
|
@ -5285,7 +5282,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
|||
double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
|
||||
double FullDETBufferingTimeYStutterCriticalPlane = 0;
|
||||
double TimeToFinishSwathTransferStutterCriticalPlane = 0;
|
||||
uint k, j;
|
||||
unsigned int k, j;
|
||||
|
||||
mode_lib->vba.TotalActiveDPP = 0;
|
||||
mode_lib->vba.TotalDCCActiveDPP = 0;
|
||||
|
@ -5507,7 +5504,7 @@ static void CalculateDCFCLKDeepSleep(
|
|||
double DPPCLK[],
|
||||
double *DCFCLKDeepSleep)
|
||||
{
|
||||
uint k;
|
||||
unsigned int k;
|
||||
double DisplayPipeLineDeliveryTimeLuma;
|
||||
double DisplayPipeLineDeliveryTimeChroma;
|
||||
//double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
|
||||
|
@ -5727,7 +5724,7 @@ static void CalculatePixelDeliveryTimes(
|
|||
double DisplayPipeRequestDeliveryTimeChromaPrefetch[])
|
||||
{
|
||||
double req_per_swath_ub;
|
||||
uint k;
|
||||
unsigned int k;
|
||||
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (VRatio[k] <= 1) {
|
||||
|
@ -5869,7 +5866,7 @@ static void CalculateMetaAndPTETimes(
|
|||
unsigned int dpte_groups_per_row_chroma_ub;
|
||||
unsigned int num_group_per_lower_vm_stage;
|
||||
unsigned int num_req_per_lower_vm_stage;
|
||||
uint k;
|
||||
unsigned int k;
|
||||
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (GPUVMEnable == true) {
|
||||
|
|
|
@ -843,6 +843,8 @@ static int smu_sw_init(void *handle)
|
|||
smu->smu_baco.state = SMU_BACO_STATE_EXIT;
|
||||
smu->smu_baco.platform_support = false;
|
||||
|
||||
mutex_init(&smu->sensor_lock);
|
||||
|
||||
smu->watermarks_bitmap = 0;
|
||||
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
|
||||
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
|
||||
|
|
|
@ -1018,6 +1018,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
|
|||
if (!data || !size)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&smu->sensor_lock);
|
||||
switch (sensor) {
|
||||
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
|
||||
*(uint32_t *)data = pptable->FanMaximumRpm;
|
||||
|
@ -1044,6 +1045,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
|
|||
default:
|
||||
ret = smu_smc_read_sensor(smu, sensor, data, size);
|
||||
}
|
||||
mutex_unlock(&smu->sensor_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -344,6 +344,7 @@ struct smu_context
|
|||
const struct smu_funcs *funcs;
|
||||
const struct pptable_funcs *ppt_funcs;
|
||||
struct mutex mutex;
|
||||
struct mutex sensor_lock;
|
||||
uint64_t pool_size;
|
||||
|
||||
struct smu_table_context smu_table;
|
||||
|
|
|
@ -547,7 +547,7 @@ static int navi10_get_metrics_table(struct smu_context *smu,
|
|||
struct smu_table_context *smu_table= &smu->smu_table;
|
||||
int ret = 0;
|
||||
|
||||
if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
|
||||
if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
|
||||
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
|
||||
(void *)smu_table->metrics_table, false);
|
||||
if (ret) {
|
||||
|
@ -1386,6 +1386,7 @@ static int navi10_read_sensor(struct smu_context *smu,
|
|||
if(!data || !size)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&smu->sensor_lock);
|
||||
switch (sensor) {
|
||||
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
|
||||
*(uint32_t *)data = pptable->FanMaximumRpm;
|
||||
|
@ -1409,6 +1410,7 @@ static int navi10_read_sensor(struct smu_context *smu,
|
|||
default:
|
||||
ret = smu_smc_read_sensor(smu, sensor, data, size);
|
||||
}
|
||||
mutex_unlock(&smu->sensor_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -3023,6 +3023,7 @@ static int vega20_read_sensor(struct smu_context *smu,
|
|||
if(!data || !size)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&smu->sensor_lock);
|
||||
switch (sensor) {
|
||||
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
|
||||
*(uint32_t *)data = pptable->FanMaximumRpm;
|
||||
|
@ -3048,6 +3049,7 @@ static int vega20_read_sensor(struct smu_context *smu,
|
|||
default:
|
||||
ret = smu_smc_read_sensor(smu, sensor, data, size);
|
||||
}
|
||||
mutex_unlock(&smu->sensor_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -43,9 +43,8 @@ komeda_wb_encoder_atomic_check(struct drm_encoder *encoder,
|
|||
struct komeda_data_flow_cfg dflow;
|
||||
int err;
|
||||
|
||||
if (!writeback_job || !writeback_job->fb) {
|
||||
if (!writeback_job)
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!crtc_st->active) {
|
||||
DRM_DEBUG_ATOMIC("Cannot write the composition result out on a inactive CRTC.\n");
|
||||
|
@ -166,8 +165,10 @@ static int komeda_wb_connector_add(struct komeda_kms_dev *kms,
|
|||
&komeda_wb_encoder_helper_funcs,
|
||||
formats, n_formats);
|
||||
komeda_put_fourcc_list(formats);
|
||||
if (err)
|
||||
if (err) {
|
||||
kfree(kwb_conn);
|
||||
return err;
|
||||
}
|
||||
|
||||
drm_connector_helper_add(&wb_conn->base, &komeda_wb_conn_helper_funcs);
|
||||
|
||||
|
|
|
@ -131,7 +131,7 @@ malidp_mw_encoder_atomic_check(struct drm_encoder *encoder,
|
|||
struct drm_framebuffer *fb;
|
||||
int i, n_planes;
|
||||
|
||||
if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
|
||||
if (!conn_state->writeback_job)
|
||||
return 0;
|
||||
|
||||
fb = conn_state->writeback_job->fb;
|
||||
|
@ -248,7 +248,7 @@ void malidp_mw_atomic_commit(struct drm_device *drm,
|
|||
|
||||
mw_state = to_mw_state(conn_state);
|
||||
|
||||
if (conn_state->writeback_job && conn_state->writeback_job->fb) {
|
||||
if (conn_state->writeback_job) {
|
||||
struct drm_framebuffer *fb = conn_state->writeback_job->fb;
|
||||
|
||||
DRM_DEV_DEBUG_DRIVER(drm->dev,
|
||||
|
|
|
@ -430,10 +430,15 @@ static int drm_atomic_connector_check(struct drm_connector *connector,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (writeback_job->out_fence && !writeback_job->fb) {
|
||||
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] requesting out-fence without framebuffer\n",
|
||||
connector->base.id, connector->name);
|
||||
return -EINVAL;
|
||||
if (!writeback_job->fb) {
|
||||
if (writeback_job->out_fence) {
|
||||
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] requesting out-fence without framebuffer\n",
|
||||
connector->base.id, connector->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
drm_writeback_cleanup_job(writeback_job);
|
||||
state->writeback_job = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -324,6 +324,9 @@ void drm_writeback_cleanup_job(struct drm_writeback_job *job)
|
|||
if (job->fb)
|
||||
drm_framebuffer_put(job->fb);
|
||||
|
||||
if (job->out_fence)
|
||||
dma_fence_put(job->out_fence);
|
||||
|
||||
kfree(job);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_writeback_cleanup_job);
|
||||
|
@ -366,25 +369,29 @@ drm_writeback_signal_completion(struct drm_writeback_connector *wb_connector,
|
|||
{
|
||||
unsigned long flags;
|
||||
struct drm_writeback_job *job;
|
||||
struct dma_fence *out_fence;
|
||||
|
||||
spin_lock_irqsave(&wb_connector->job_lock, flags);
|
||||
job = list_first_entry_or_null(&wb_connector->job_queue,
|
||||
struct drm_writeback_job,
|
||||
list_entry);
|
||||
if (job) {
|
||||
if (job)
|
||||
list_del(&job->list_entry);
|
||||
if (job->out_fence) {
|
||||
if (status)
|
||||
dma_fence_set_error(job->out_fence, status);
|
||||
dma_fence_signal(job->out_fence);
|
||||
dma_fence_put(job->out_fence);
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&wb_connector->job_lock, flags);
|
||||
|
||||
if (WARN_ON(!job))
|
||||
return;
|
||||
|
||||
out_fence = job->out_fence;
|
||||
if (out_fence) {
|
||||
if (status)
|
||||
dma_fence_set_error(out_fence, status);
|
||||
dma_fence_signal(out_fence);
|
||||
dma_fence_put(out_fence);
|
||||
job->out_fence = NULL;
|
||||
}
|
||||
|
||||
INIT_WORK(&job->cleanup_work, cleanup_work);
|
||||
queue_work(system_long_wq, &job->cleanup_work);
|
||||
}
|
||||
|
|
|
@ -7261,7 +7261,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
|
|||
pipe_config->fdi_lanes = lane;
|
||||
|
||||
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
|
||||
link_bw, &pipe_config->fdi_m_n, false);
|
||||
link_bw, &pipe_config->fdi_m_n, false, false);
|
||||
|
||||
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
|
||||
if (ret == -EDEADLK)
|
||||
|
@ -7508,11 +7508,15 @@ void
|
|||
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
|
||||
int pixel_clock, int link_clock,
|
||||
struct intel_link_m_n *m_n,
|
||||
bool constant_n)
|
||||
bool constant_n, bool fec_enable)
|
||||
{
|
||||
m_n->tu = 64;
|
||||
u32 data_clock = bits_per_pixel * pixel_clock;
|
||||
|
||||
compute_m_n(bits_per_pixel * pixel_clock,
|
||||
if (fec_enable)
|
||||
data_clock = intel_dp_mode_to_fec_clock(data_clock);
|
||||
|
||||
m_n->tu = 64;
|
||||
compute_m_n(data_clock,
|
||||
link_clock * nlanes * 8,
|
||||
&m_n->gmch_m, &m_n->gmch_n,
|
||||
constant_n);
|
||||
|
|
|
@ -414,7 +414,7 @@ enum phy_fia {
|
|||
void intel_link_compute_m_n(u16 bpp, int nlanes,
|
||||
int pixel_clock, int link_clock,
|
||||
struct intel_link_m_n *m_n,
|
||||
bool constant_n);
|
||||
bool constant_n, bool fec_enable);
|
||||
bool is_ccs_modifier(u64 modifier);
|
||||
void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
|
||||
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
|
||||
|
|
|
@ -78,8 +78,8 @@
|
|||
#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
|
||||
#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
|
||||
|
||||
/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
|
||||
#define DP_DSC_FEC_OVERHEAD_FACTOR 976
|
||||
/* DP DSC FEC Overhead factor = 1/(0.972261) */
|
||||
#define DP_DSC_FEC_OVERHEAD_FACTOR 972261
|
||||
|
||||
/* Compliance test status bits */
|
||||
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
|
||||
|
@ -494,6 +494,97 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
|
|||
return 0;
|
||||
}
|
||||
|
||||
u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
|
||||
{
|
||||
return div_u64(mul_u32_u32(mode_clock, 1000000U),
|
||||
DP_DSC_FEC_OVERHEAD_FACTOR);
|
||||
}
|
||||
|
||||
static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
|
||||
u32 mode_clock, u32 mode_hdisplay)
|
||||
{
|
||||
u32 bits_per_pixel, max_bpp_small_joiner_ram;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
|
||||
* (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
|
||||
* for SST -> TimeSlotsPerMTP is 1,
|
||||
* for MST -> TimeSlotsPerMTP has to be calculated
|
||||
*/
|
||||
bits_per_pixel = (link_clock * lane_count * 8) /
|
||||
intel_dp_mode_to_fec_clock(mode_clock);
|
||||
DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
|
||||
|
||||
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
|
||||
max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay;
|
||||
DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
|
||||
|
||||
/*
|
||||
* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
|
||||
* check, output bpp from small joiner RAM check)
|
||||
*/
|
||||
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
|
||||
|
||||
/* Error out if the max bpp is less than smallest allowed valid bpp */
|
||||
if (bits_per_pixel < valid_dsc_bpp[0]) {
|
||||
DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
|
||||
bits_per_pixel, valid_dsc_bpp[0]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Find the nearest match in the array of known BPPs from VESA */
|
||||
for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
|
||||
if (bits_per_pixel < valid_dsc_bpp[i + 1])
|
||||
break;
|
||||
}
|
||||
bits_per_pixel = valid_dsc_bpp[i];
|
||||
|
||||
/*
|
||||
* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
|
||||
* fractional part is 0
|
||||
*/
|
||||
return bits_per_pixel << 4;
|
||||
}
|
||||
|
||||
static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
|
||||
int mode_clock, int mode_hdisplay)
|
||||
{
|
||||
u8 min_slice_count, i;
|
||||
int max_slice_width;
|
||||
|
||||
if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
|
||||
min_slice_count = DIV_ROUND_UP(mode_clock,
|
||||
DP_DSC_MAX_ENC_THROUGHPUT_0);
|
||||
else
|
||||
min_slice_count = DIV_ROUND_UP(mode_clock,
|
||||
DP_DSC_MAX_ENC_THROUGHPUT_1);
|
||||
|
||||
max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
|
||||
if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
|
||||
DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
|
||||
max_slice_width);
|
||||
return 0;
|
||||
}
|
||||
/* Also take into account max slice width */
|
||||
min_slice_count = min_t(u8, min_slice_count,
|
||||
DIV_ROUND_UP(mode_hdisplay,
|
||||
max_slice_width));
|
||||
|
||||
/* Find the closest match to the valid slice count values */
|
||||
for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
|
||||
if (valid_dsc_slicecount[i] >
|
||||
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
|
||||
false))
|
||||
break;
|
||||
if (min_slice_count <= valid_dsc_slicecount[i])
|
||||
return valid_dsc_slicecount[i];
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static enum drm_mode_status
|
||||
intel_dp_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
|
@ -2226,7 +2317,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
|
|||
adjusted_mode->crtc_clock,
|
||||
pipe_config->port_clock,
|
||||
&pipe_config->dp_m_n,
|
||||
constant_n);
|
||||
constant_n, pipe_config->fec_enable);
|
||||
|
||||
if (intel_connector->panel.downclock_mode != NULL &&
|
||||
dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
|
||||
|
@ -2236,7 +2327,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
|
|||
intel_connector->panel.downclock_mode->clock,
|
||||
pipe_config->port_clock,
|
||||
&pipe_config->dp_m2_n2,
|
||||
constant_n);
|
||||
constant_n, pipe_config->fec_enable);
|
||||
}
|
||||
|
||||
if (!HAS_DDI(dev_priv))
|
||||
|
@ -4323,91 +4414,6 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
|
|||
DP_DPRX_ESI_LEN;
|
||||
}
|
||||
|
||||
u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
|
||||
int mode_clock, int mode_hdisplay)
|
||||
{
|
||||
u16 bits_per_pixel, max_bpp_small_joiner_ram;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
|
||||
* (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
|
||||
* FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
|
||||
* for MST -> TimeSlotsPerMTP has to be calculated
|
||||
*/
|
||||
bits_per_pixel = (link_clock * lane_count * 8 *
|
||||
DP_DSC_FEC_OVERHEAD_FACTOR) /
|
||||
mode_clock;
|
||||
|
||||
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
|
||||
max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
|
||||
mode_hdisplay;
|
||||
|
||||
/*
|
||||
* Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
|
||||
* check, output bpp from small joiner RAM check)
|
||||
*/
|
||||
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
|
||||
|
||||
/* Error out if the max bpp is less than smallest allowed valid bpp */
|
||||
if (bits_per_pixel < valid_dsc_bpp[0]) {
|
||||
DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Find the nearest match in the array of known BPPs from VESA */
|
||||
for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
|
||||
if (bits_per_pixel < valid_dsc_bpp[i + 1])
|
||||
break;
|
||||
}
|
||||
bits_per_pixel = valid_dsc_bpp[i];
|
||||
|
||||
/*
|
||||
* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
|
||||
* fractional part is 0
|
||||
*/
|
||||
return bits_per_pixel << 4;
|
||||
}
|
||||
|
||||
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
|
||||
int mode_clock,
|
||||
int mode_hdisplay)
|
||||
{
|
||||
u8 min_slice_count, i;
|
||||
int max_slice_width;
|
||||
|
||||
if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
|
||||
min_slice_count = DIV_ROUND_UP(mode_clock,
|
||||
DP_DSC_MAX_ENC_THROUGHPUT_0);
|
||||
else
|
||||
min_slice_count = DIV_ROUND_UP(mode_clock,
|
||||
DP_DSC_MAX_ENC_THROUGHPUT_1);
|
||||
|
||||
max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
|
||||
if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
|
||||
DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
|
||||
max_slice_width);
|
||||
return 0;
|
||||
}
|
||||
/* Also take into account max slice width */
|
||||
min_slice_count = min_t(u8, min_slice_count,
|
||||
DIV_ROUND_UP(mode_hdisplay,
|
||||
max_slice_width));
|
||||
|
||||
/* Find the closest match to the valid slice count values */
|
||||
for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
|
||||
if (valid_dsc_slicecount[i] >
|
||||
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
|
||||
false))
|
||||
break;
|
||||
if (min_slice_count <= valid_dsc_slicecount[i])
|
||||
return valid_dsc_slicecount[i];
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
|
|
|
@ -102,10 +102,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
|
|||
bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
|
||||
bool
|
||||
intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
|
||||
u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
|
||||
int mode_clock, int mode_hdisplay);
|
||||
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
|
||||
int mode_hdisplay);
|
||||
|
||||
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
|
||||
bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
|
||||
|
@ -118,4 +114,6 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
|
|||
return ~((1 << lane_count) - 1) & 0xf;
|
||||
}
|
||||
|
||||
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
|
||||
|
||||
#endif /* __INTEL_DP_H__ */
|
||||
|
|
|
@ -81,7 +81,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
|
|||
adjusted_mode->crtc_clock,
|
||||
crtc_state->port_clock,
|
||||
&crtc_state->dp_m_n,
|
||||
constant_n);
|
||||
constant_n, crtc_state->fec_enable);
|
||||
crtc_state->dp_m_n.tu = slots;
|
||||
|
||||
return 0;
|
||||
|
@ -615,7 +615,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
|
|||
intel_encoder->type = INTEL_OUTPUT_DP_MST;
|
||||
intel_encoder->power_domain = intel_dig_port->base.power_domain;
|
||||
intel_encoder->port = intel_dig_port->base.port;
|
||||
intel_encoder->crtc_mask = BIT(pipe);
|
||||
intel_encoder->crtc_mask = 0x7;
|
||||
intel_encoder->cloneable = 0;
|
||||
|
||||
intel_encoder->compute_config = intel_dp_mst_compute_config;
|
||||
|
|
|
@ -1528,6 +1528,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
|
|||
int src_x, src_w, src_h, crtc_w, crtc_h;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
unsigned int stride = plane_state->color_plane[0].stride;
|
||||
unsigned int cpp = fb->format->cpp[0];
|
||||
unsigned int width_bytes;
|
||||
int min_width, min_height;
|
||||
|
@ -1569,9 +1570,9 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (width_bytes > 4096 || fb->pitches[0] > 4096) {
|
||||
if (stride > 4096) {
|
||||
DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
|
||||
fb->pitches[0], 4096);
|
||||
stride, 4096);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
@ -1083,7 +1083,7 @@ static const struct dss_features omap34xx_dss_feats = {
|
|||
|
||||
static const struct dss_features omap3630_dss_feats = {
|
||||
.model = DSS_MODEL_OMAP3,
|
||||
.fck_div_max = 32,
|
||||
.fck_div_max = 31,
|
||||
.fck_freq_max = 173000000,
|
||||
.dss_fck_multiplier = 1,
|
||||
.parent_clk_name = "dpll4_ck",
|
||||
|
|
|
@ -147,7 +147,7 @@ static int rcar_du_wb_enc_atomic_check(struct drm_encoder *encoder,
|
|||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_framebuffer *fb;
|
||||
|
||||
if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
|
||||
if (!conn_state->writeback_job)
|
||||
return 0;
|
||||
|
||||
fb = conn_state->writeback_job->fb;
|
||||
|
@ -221,7 +221,7 @@ void rcar_du_writeback_setup(struct rcar_du_crtc *rcrtc,
|
|||
unsigned int i;
|
||||
|
||||
state = rcrtc->writeback.base.state;
|
||||
if (!state || !state->writeback_job || !state->writeback_job->fb)
|
||||
if (!state || !state->writeback_job)
|
||||
return;
|
||||
|
||||
fb = state->writeback_job->fb;
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
|
|
|
@ -231,7 +231,7 @@ static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
|
|||
int i;
|
||||
|
||||
conn_state = drm_atomic_get_new_connector_state(state, conn);
|
||||
if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
|
||||
if (!conn_state->writeback_job)
|
||||
return 0;
|
||||
|
||||
crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
|
||||
|
@ -271,8 +271,7 @@ static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
|
|||
u32 ctrl;
|
||||
int i;
|
||||
|
||||
if (WARN_ON(!conn_state->writeback_job ||
|
||||
!conn_state->writeback_job->fb))
|
||||
if (WARN_ON(!conn_state->writeback_job))
|
||||
return;
|
||||
|
||||
mode = &conn_state->crtc->state->adjusted_mode;
|
||||
|
|
|
@ -1003,6 +1003,8 @@ struct drm_amdgpu_info_device {
|
|||
__u64 high_va_max;
|
||||
/* gfx10 pa_sc_tile_steering_override */
|
||||
__u32 pa_sc_tile_steering_override;
|
||||
/* disabled TCCs */
|
||||
__u64 tcc_disabled_mask;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
|
|
Loading…
Reference in New Issue
Block a user