forked from luck/tmp_suning_uos_patched
MIPS: lantiq: fix early printk
The code was using a 32bit write operations in the early_printk code. This resulted in 3 zero bytes also being written to the serial port. This patch changes the memory access to 8bit. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3721/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -34,6 +34,12 @@
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#define LTQ_ASC1_BASE_ADDR 0x1E100C00
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#define LTQ_ASC_SIZE 0x400
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/*
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* during early_printk no ioremap is possible
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* lets use KSEG1 instead
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*/
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#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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/* RCU - reset control unit */
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#define LTQ_RCU_BASE_ADDR 0x1F203000
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#define LTQ_RCU_SIZE 0x1000
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@ -6,17 +6,16 @@
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <lantiq.h>
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#include <lantiq_soc.h>
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/* no ioremap possible at this early stage, lets use KSEG1 instead */
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#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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#define ASC_BUF 1024
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#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048))
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#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020))
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#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048))
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#ifdef __BIG_ENDIAN
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#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
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#else
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#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020))
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#endif
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#define TXMASK 0x3F00
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#define TXOFFSET 8
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@ -27,7 +26,7 @@ void prom_putchar(char c)
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local_irq_save(flags);
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do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
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if (c == '\n')
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ltq_w32('\r', LTQ_ASC_TBUF);
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ltq_w32(c, LTQ_ASC_TBUF);
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ltq_w8('\r', LTQ_ASC_TBUF);
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ltq_w8(c, LTQ_ASC_TBUF);
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local_irq_restore(flags);
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}
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