forked from luck/tmp_suning_uos_patched
ahci: reimplement port_map handling
Reimplement port_map handling such that 1. Non-zero PORTS_IMPL value is always examined and used if consistent with cap.n_ports. 2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and force port_map to be ((1 << cap.n_ports) - 1). 3. There were two separate places dealing with port_map. Unify them to one. As all newer ahci chips seem to get PI correct and older ones usually have zero PI. Controllers with holes in PI are very unlikely to screw up PI, so #2 makes more sense than following inconsistent PI. Without this change, not setting ATA_FLAG_HONOR_PI when it's needed results in weird detection failure. This changed logic should be able to handle all known cases correctly automatically. Verified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9, JMB360 and JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Tejun Heo
Jeff Garzik
parent
05027adccc
commit
7a234aff3d
@ -77,11 +77,10 @@ enum {
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RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
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board_ahci = 0,
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board_ahci_pi = 1,
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board_ahci_vt8251 = 2,
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board_ahci_ign_iferr = 3,
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board_ahci_sb600 = 4,
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board_ahci_mv = 5,
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board_ahci_vt8251 = 1,
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board_ahci_ign_iferr = 2,
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board_ahci_sb600 = 3,
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board_ahci_mv = 4,
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/* global controller registers */
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HOST_CAP = 0x00, /* host capabilities */
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@ -170,7 +169,6 @@ enum {
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/* ap->flags bits */
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AHCI_FLAG_NO_NCQ = (1 << 24),
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AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
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AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
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AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
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AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
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AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
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@ -332,14 +330,6 @@ static const struct ata_port_info ahci_port_info[] = {
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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/* board_ahci_pi */
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{
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.flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
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.link_flags = AHCI_LFLAG_COMMON,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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/* board_ahci_vt8251 */
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{
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.flags = AHCI_FLAG_COMMON | AHCI_FLAG_NO_NCQ,
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@ -371,8 +361,8 @@ static const struct ata_port_info ahci_port_info[] = {
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.sht = &ahci_sht,
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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AHCI_FLAG_HONOR_PI | AHCI_FLAG_NO_NCQ |
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AHCI_FLAG_NO_MSI | AHCI_FLAG_MV_PATA,
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AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
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AHCI_FLAG_MV_PATA,
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.link_flags = AHCI_LFLAG_COMMON,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = ATA_UDMA6,
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@ -392,23 +382,23 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
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{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
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{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
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{ PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
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{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
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{ PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
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{ PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
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{ PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
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{ PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
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{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
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{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
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{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
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{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
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{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
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{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
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{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
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/* JMicron 360/1/3/5/6, match class to avoid IDE function */
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{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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@ -562,16 +552,6 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
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cap &= ~HOST_CAP_NCQ;
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}
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/* fixup zero port_map */
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if (!port_map) {
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port_map = (1 << ahci_nr_ports(cap)) - 1;
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dev_printk(KERN_WARNING, &pdev->dev,
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"PORTS_IMPL is zero, forcing 0x%x\n", port_map);
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/* write the fixed up value to the PI register */
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hpriv->saved_port_map = port_map;
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}
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/*
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* Temporary Marvell 6145 hack: PATA port presence
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* is asserted through the standard AHCI port
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@ -587,7 +567,7 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
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}
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/* cross check port_map and cap.n_ports */
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if (pi->flags & AHCI_FLAG_HONOR_PI) {
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if (port_map) {
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u32 tmp_port_map = port_map;
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int n_ports = ahci_nr_ports(cap);
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@ -598,17 +578,26 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
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}
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}
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/* Whine if inconsistent. No need to update cap.
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* port_map is used to determine number of ports.
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/* If n_ports and port_map are inconsistent, whine and
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* clear port_map and let it be generated from n_ports.
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*/
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if (n_ports || tmp_port_map)
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if (n_ports || tmp_port_map) {
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dev_printk(KERN_WARNING, &pdev->dev,
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"nr_ports (%u) and implemented port map "
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"(0x%x) don't match\n",
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"(0x%x) don't match, using nr_ports\n",
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ahci_nr_ports(cap), port_map);
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} else {
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/* fabricate port_map from cap.nr_ports */
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port_map = 0;
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}
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}
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/* fabricate port_map from cap.nr_ports */
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if (!port_map) {
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port_map = (1 << ahci_nr_ports(cap)) - 1;
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dev_printk(KERN_WARNING, &pdev->dev,
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"forcing PORTS_IMPL to 0x%x\n", port_map);
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/* write the fixed up value to the PI register */
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hpriv->saved_port_map = port_map;
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}
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/* record values to use during operation */
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