forked from luck/tmp_suning_uos_patched
clk: renesas: Updates for v5.10 (take two)
- Add support for the new R-Car V3U (R8A779A0) SoC, - Minor fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCX2So6QAKCRCKwlD9ZEnx cBNcAQDFbFJIW1Zs+bLySoJxTNd5co7w78XFF2HCGH1Ihh7i9AD/RLX7LytqDzuN uSEJF5T4nWCLhMe6d2Cd3l5araqCbgI= =Gl66 -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new R-Car V3U (R8A779A0) SoC - Add support for the VSP for Resizing clock on RZ/G1H, - Fix VSP clock names to match corrected hardware documentation. - Minor fixes and improvements * tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3: Update description for RZ/G2 clk: renesas: cpg-mssr: Add support for R-Car V3U clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0 dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions dt-bindings: power: Add r8a779a0 SYSC power domain definitions clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) clk: renesas: r8a7742: Add clk entry for VSPR
This commit is contained in:
Stephen Boyd
commit
7aa908b48d
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@ -47,6 +47,7 @@ properties:
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- renesas,r8a77980-cpg-mssr # R-Car V3H
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- renesas,r8a77990-cpg-mssr # R-Car E3
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- renesas,r8a77995-cpg-mssr # R-Car D3
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- renesas,r8a779a0-cpg-mssr # R-Car V3U
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reg:
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maxItems: 1
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@ -30,6 +30,7 @@ config CLK_RENESAS
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select CLK_R8A77980 if ARCH_R8A77980
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select CLK_R8A77990 if ARCH_R8A77990
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select CLK_R8A77995 if ARCH_R8A77995
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select CLK_R8A779A0 if ARCH_R8A779A0
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select CLK_R9A06G032 if ARCH_R9A06G032
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select CLK_SH73A0 if ARCH_SH73A0
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@ -145,6 +146,10 @@ config CLK_R8A77995
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bool "R-Car D3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A779A0
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bool "R-Car V3U clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_R9A06G032
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bool "Renesas R9A06G032 clock driver"
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help
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@ -162,7 +167,7 @@ config CLK_RCAR_GEN2_CPG
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select CLK_RENESAS_CPG_MSSR
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config CLK_RCAR_GEN3_CPG
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bool "R-Car Gen3 CPG clock support" if COMPILE_TEST
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bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_RCAR_USB2_CLOCK_SEL
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@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
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obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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@ -214,7 +214,7 @@ const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
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.cpg_clk_register = rza2_cpg_clk_register,
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/* RZ/A2 has Standby Control Registers */
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.stbyctrl = true,
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.reg_layout = CLK_REG_LAYOUT_RZ_A,
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};
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static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
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@ -97,7 +97,8 @@ static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
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DEF_MOD("tmu0", 125, R8A7742_CLK_CP),
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DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS),
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DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS),
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DEF_MOD("vspr", 130, R8A7742_CLK_ZS),
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DEF_MOD("vsps", 131, R8A7742_CLK_ZS),
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DEF_MOD("scifa2", 202, R8A7742_CLK_MP),
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DEF_MOD("scifa1", 203, R8A7742_CLK_MP),
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DEF_MOD("scifa0", 204, R8A7742_CLK_MP),
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@ -92,7 +92,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
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DEF_MOD("tmu0", 125, R8A7743_CLK_CP),
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DEF_MOD("vsp1du1", 127, R8A7743_CLK_ZS),
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DEF_MOD("vsp1du0", 128, R8A7743_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7743_CLK_ZS),
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DEF_MOD("vsps", 131, R8A7743_CLK_ZS),
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DEF_MOD("scifa2", 202, R8A7743_CLK_MP),
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DEF_MOD("scifa1", 203, R8A7743_CLK_MP),
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DEF_MOD("scifa0", 204, R8A7743_CLK_MP),
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@ -90,7 +90,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
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DEF_MOD("cmt0", 124, R8A7745_CLK_R),
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DEF_MOD("tmu0", 125, R8A7745_CLK_CP),
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DEF_MOD("vsp1du0", 128, R8A7745_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7745_CLK_ZS),
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DEF_MOD("vsps", 131, R8A7745_CLK_ZS),
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DEF_MOD("scifa2", 202, R8A7745_CLK_MP),
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DEF_MOD("scifa1", 203, R8A7745_CLK_MP),
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DEF_MOD("scifa0", 204, R8A7745_CLK_MP),
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@ -85,7 +85,7 @@ static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
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DEF_MOD("tmu2", 122, R8A77470_CLK_P),
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DEF_MOD("cmt0", 124, R8A77470_CLK_R),
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DEF_MOD("vsp1du0", 128, R8A77470_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A77470_CLK_ZS),
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DEF_MOD("vsps", 131, R8A77470_CLK_ZS),
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DEF_MOD("msiof2", 205, R8A77470_CLK_MP),
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DEF_MOD("msiof1", 208, R8A77470_CLK_MP),
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DEF_MOD("sys-dmac1", 218, R8A77470_CLK_ZS),
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@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
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DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
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DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
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DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
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DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
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DEF_MOD("vspr", 130, R8A7790_CLK_ZS),
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DEF_MOD("vsps", 131, R8A7790_CLK_ZS),
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DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
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DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
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DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
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@ -102,7 +102,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
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DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
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DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
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DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
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DEF_MOD("vsps", 131, R8A7791_CLK_ZS),
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DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
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DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
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DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
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@ -88,7 +88,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
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DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
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DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
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DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
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DEF_MOD("vsps", 131, R8A7792_CLK_ZS),
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DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
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DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
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DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
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@ -97,7 +97,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
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DEF_MOD("cmt0", 124, R8A7794_CLK_R),
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DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
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DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
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DEF_MOD("vsps", 131, R8A7794_CLK_ZS),
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DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
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DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
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DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
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276
drivers/clk/renesas/r8a779a0-cpg-mssr.c
Normal file
276
drivers/clk/renesas/r8a779a0-cpg-mssr.c
Normal file
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@ -0,0 +1,276 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/bug.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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enum rcar_r8a779a0_clk_types {
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CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_R8A779A0_PLL1,
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CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
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CLK_TYPE_R8A779A0_PLL5,
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CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
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};
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struct rcar_r8a779a0_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll5_mult;
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u8 pll5_div;
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u8 osc_prediv;
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};
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL1,
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CLK_PLL20,
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CLK_PLL21,
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CLK_PLL30,
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CLK_PLL31,
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CLK_PLL5,
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CLK_PLL1_DIV2,
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CLK_PLL20_DIV2,
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CLK_PLL21_DIV2,
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CLK_PLL30_DIV2,
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CLK_PLL31_DIV2,
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CLK_PLL5_DIV2,
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CLK_PLL5_DIV4,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_OCO,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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#define DEF_PLL(_name, _id, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
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.offset = _offset)
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static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
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DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
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DEF_PLL(".pll20", CLK_PLL20, 0x0834),
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DEF_PLL(".pll21", CLK_PLL21, 0x0838),
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DEF_PLL(".pll30", CLK_PLL30, 0x083c),
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DEF_PLL(".pll31", CLK_PLL31, 0x0840),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
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DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1),
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DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1),
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DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1),
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DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
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DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
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DEF_RATE(".oco", CLK_OCO, 32768),
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/* Core Clock Outputs */
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DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
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DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1),
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DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1),
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DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1),
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DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
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DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1),
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DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
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DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
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DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
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DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
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DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
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DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
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DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_MAIN, 2, 1),
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DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
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DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
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DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
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DEF_GEN3_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
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DEF_GEN3_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
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};
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static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
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DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
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DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
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DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
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DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
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};
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static spinlock_t cpg_lock;
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static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
|
||||
static unsigned int cpg_clk_extalr __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base,
|
||||
struct raw_notifier_head *notifiers)
|
||||
{
|
||||
const struct clk *parent;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
u32 value;
|
||||
|
||||
parent = clks[core->parent & 0xffff]; /* some types use high bits */
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_R8A779A0_MAIN:
|
||||
div = cpg_pll_config->extal_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
div = cpg_pll_config->pll1_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL2X_3X:
|
||||
value = readl(base + core->offset);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL5:
|
||||
mult = cpg_pll_config->pll5_mult;
|
||||
div = cpg_pll_config->pll5_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_MDSEL:
|
||||
/*
|
||||
* Clock selectable between two parents and two fixed dividers
|
||||
* using a mode pin
|
||||
*/
|
||||
if (cpg_mode & BIT(core->offset)) {
|
||||
div = core->div & 0xffff;
|
||||
} else {
|
||||
parent = clks[core->parent >> 16];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
div = core->div >> 16;
|
||||
}
|
||||
mult = 1;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_OSC:
|
||||
/*
|
||||
* Clock combining OSC EXTAL predivider and a fixed divider
|
||||
*/
|
||||
div = cpg_pll_config->osc_prediv * core->div;
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return clk_register_fixed_factor(NULL, core->name,
|
||||
__clk_get_name(parent), 0, mult, div);
|
||||
}
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
/*
|
||||
* MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
|
||||
* 14 13 (MHz) 21 31
|
||||
* --------------------------------------------------------
|
||||
* 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
|
||||
* 0 1 20 x 1 x106 x180 x106 x120 x160 /19
|
||||
* 1 0 Prohibited setting
|
||||
* 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
|
||||
{ 1, 128, 1, 192, 1, 16, },
|
||||
{ 1, 106, 1, 160, 1, 19, },
|
||||
{ 0, 0, 0, 0, 0, 0, },
|
||||
{ 2, 128, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a779a0_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
cpg_clk_extalr = CLK_EXTALR;
|
||||
spin_lock_init(&cpg_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a779a0_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a779a0_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
|
||||
.num_hw_mod_clks = 15 * 32,
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a779a0_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
|
||||
|
||||
.reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
|
||||
};
|
||||
|
|
@ -57,8 +57,10 @@ static const u16 mstpsr[] = {
|
|||
0x9A0, 0x9A4, 0x9A8, 0x9AC,
|
||||
};
|
||||
|
||||
#define MSTPSR(i) mstpsr[i]
|
||||
|
||||
static const u16 mstpsr_for_v3u[] = {
|
||||
0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
|
||||
0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
|
||||
};
|
||||
|
||||
/*
|
||||
* System Module Stop Control Register offsets
|
||||
|
|
@ -69,7 +71,10 @@ static const u16 smstpcr[] = {
|
|||
0x990, 0x994, 0x998, 0x99C,
|
||||
};
|
||||
|
||||
#define SMSTPCR(i) smstpcr[i]
|
||||
static const u16 mstpcr_for_v3u[] = {
|
||||
0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
|
||||
0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
|
||||
};
|
||||
|
||||
/*
|
||||
* Standby Control Register offsets (RZ/A)
|
||||
|
|
@ -81,8 +86,6 @@ static const u16 stbcr[] = {
|
|||
0x424, 0x428, 0x42C,
|
||||
};
|
||||
|
||||
#define STBCR(i) stbcr[i]
|
||||
|
||||
/*
|
||||
* Software Reset Register offsets
|
||||
*/
|
||||
|
|
@ -92,8 +95,10 @@ static const u16 srcr[] = {
|
|||
0x920, 0x924, 0x928, 0x92C,
|
||||
};
|
||||
|
||||
#define SRCR(i) srcr[i]
|
||||
|
||||
static const u16 srcr_for_v3u[] = {
|
||||
0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
|
||||
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
|
||||
};
|
||||
|
||||
/* Realtime Module Stop Control Register offsets */
|
||||
#define RMSTPCR(i) (smstpcr[i] - 0x20)
|
||||
|
|
@ -102,8 +107,16 @@ static const u16 srcr[] = {
|
|||
#define MMSTPCR(i) (smstpcr[i] + 0x20)
|
||||
|
||||
/* Software Reset Clearing Register offsets */
|
||||
#define SRSTCLR(i) (0x940 + (i) * 4)
|
||||
|
||||
static const u16 srstclr[] = {
|
||||
0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
|
||||
0x960, 0x964, 0x968, 0x96C,
|
||||
};
|
||||
|
||||
static const u16 srstclr_for_v3u[] = {
|
||||
0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
|
||||
0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
|
||||
};
|
||||
|
||||
/**
|
||||
* Clock Pulse Generator / Module Standby and Software Reset Private Data
|
||||
|
|
@ -111,13 +124,17 @@ static const u16 srcr[] = {
|
|||
* @rcdev: Optional reset controller entity
|
||||
* @dev: CPG/MSSR device
|
||||
* @base: CPG/MSSR register block base address
|
||||
* @reg_layout: CPG/MSSR register layout
|
||||
* @rmw_lock: protects RMW register accesses
|
||||
* @np: Device node in DT for this CPG/MSSR module
|
||||
* @num_core_clks: Number of Core Clocks in clks[]
|
||||
* @num_mod_clks: Number of Module Clocks in clks[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @stbyctrl: This device has Standby Control Registers
|
||||
* @notifiers: Notifier chain to save/restore clock state for system resume
|
||||
* @status_regs: Pointer to status registers array
|
||||
* @control_regs: Pointer to control registers array
|
||||
* @reset_regs: Pointer to reset registers array
|
||||
* @reset_clear_regs: Pointer to reset clearing registers array
|
||||
* @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
|
||||
* @smstpcr_saved[].val: Saved values of SMSTPCR[]
|
||||
* @clks: Array containing all Core and Module Clocks
|
||||
|
|
@ -128,19 +145,23 @@ struct cpg_mssr_priv {
|
|||
#endif
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
enum clk_reg_layout reg_layout;
|
||||
spinlock_t rmw_lock;
|
||||
struct device_node *np;
|
||||
|
||||
unsigned int num_core_clks;
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
bool stbyctrl;
|
||||
|
||||
struct raw_notifier_head notifiers;
|
||||
const u16 *status_regs;
|
||||
const u16 *control_regs;
|
||||
const u16 *reset_regs;
|
||||
const u16 *reset_clear_regs;
|
||||
struct {
|
||||
u32 mask;
|
||||
u32 val;
|
||||
} smstpcr_saved[ARRAY_SIZE(smstpcr)];
|
||||
} smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
|
||||
|
||||
struct clk *clks[];
|
||||
};
|
||||
|
|
@ -177,40 +198,40 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
|
|||
enable ? "ON" : "OFF");
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
|
||||
if (priv->stbyctrl) {
|
||||
value = readb(priv->base + STBCR(reg));
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
|
||||
value = readb(priv->base + priv->control_regs[reg]);
|
||||
if (enable)
|
||||
value &= ~bitmask;
|
||||
else
|
||||
value |= bitmask;
|
||||
writeb(value, priv->base + STBCR(reg));
|
||||
writeb(value, priv->base + priv->control_regs[reg]);
|
||||
|
||||
/* dummy read to ensure write has completed */
|
||||
readb(priv->base + STBCR(reg));
|
||||
barrier_data(priv->base + STBCR(reg));
|
||||
readb(priv->base + priv->control_regs[reg]);
|
||||
barrier_data(priv->base + priv->control_regs[reg]);
|
||||
} else {
|
||||
value = readl(priv->base + SMSTPCR(reg));
|
||||
value = readl(priv->base + priv->control_regs[reg]);
|
||||
if (enable)
|
||||
value &= ~bitmask;
|
||||
else
|
||||
value |= bitmask;
|
||||
writel(value, priv->base + SMSTPCR(reg));
|
||||
writel(value, priv->base + priv->control_regs[reg]);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
|
||||
if (!enable || priv->stbyctrl)
|
||||
if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
|
||||
return 0;
|
||||
|
||||
for (i = 1000; i > 0; --i) {
|
||||
if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
|
||||
if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
|
||||
break;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
if (!i) {
|
||||
dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
|
||||
priv->base + SMSTPCR(reg), bit);
|
||||
priv->base + priv->control_regs[reg], bit);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
|
|
@ -233,10 +254,10 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
|
|||
struct cpg_mssr_priv *priv = clock->priv;
|
||||
u32 value;
|
||||
|
||||
if (priv->stbyctrl)
|
||||
value = readb(priv->base + STBCR(clock->index / 32));
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
|
||||
value = readb(priv->base + priv->control_regs[clock->index / 32]);
|
||||
else
|
||||
value = readl(priv->base + MSTPSR(clock->index / 32));
|
||||
value = readl(priv->base + priv->status_regs[clock->index / 32]);
|
||||
|
||||
return !(value & BIT(clock->index % 32));
|
||||
}
|
||||
|
|
@ -272,7 +293,7 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
|||
|
||||
case CPG_MOD:
|
||||
type = "module";
|
||||
if (priv->stbyctrl) {
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
|
||||
idx = MOD_CLK_PACK_10(clkidx);
|
||||
range_check = 7 - (clkidx % 10);
|
||||
} else {
|
||||
|
|
@ -578,13 +599,13 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
|
|||
dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
|
||||
|
||||
/* Reset module */
|
||||
writel(bitmask, priv->base + SRCR(reg));
|
||||
writel(bitmask, priv->base + priv->reset_regs[reg]);
|
||||
|
||||
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
|
||||
udelay(35);
|
||||
|
||||
/* Release module from reset state */
|
||||
writel(bitmask, priv->base + SRSTCLR(reg));
|
||||
writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -598,7 +619,7 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
|
|||
|
||||
dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
|
||||
|
||||
writel(bitmask, priv->base + SRCR(reg));
|
||||
writel(bitmask, priv->base + priv->reset_regs[reg]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -612,7 +633,7 @@ static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
|
|||
|
||||
dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
|
||||
|
||||
writel(bitmask, priv->base + SRSTCLR(reg));
|
||||
writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -624,7 +645,7 @@ static int cpg_mssr_status(struct reset_controller_dev *rcdev,
|
|||
unsigned int bit = id % 32;
|
||||
u32 bitmask = BIT(bit);
|
||||
|
||||
return !!(readl(priv->base + SRCR(reg)) & bitmask);
|
||||
return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops cpg_mssr_reset_ops = {
|
||||
|
|
@ -803,6 +824,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.compatible = "renesas,r8a77995-cpg-mssr",
|
||||
.data = &r8a77995_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A779A0
|
||||
{
|
||||
.compatible = "renesas,r8a779a0-cpg-mssr",
|
||||
.data = &r8a779a0_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
@ -825,9 +852,10 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
|
|||
/* Save module registers with bits under our control */
|
||||
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
|
||||
if (priv->smstpcr_saved[reg].mask)
|
||||
priv->smstpcr_saved[reg].val = priv->stbyctrl ?
|
||||
readb(priv->base + STBCR(reg)) :
|
||||
readl(priv->base + SMSTPCR(reg));
|
||||
priv->smstpcr_saved[reg].val =
|
||||
priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
|
||||
readb(priv->base + priv->control_regs[reg]) :
|
||||
readl(priv->base + priv->control_regs[reg]);
|
||||
}
|
||||
|
||||
/* Save core clocks */
|
||||
|
|
@ -855,23 +883,23 @@ static int cpg_mssr_resume_noirq(struct device *dev)
|
|||
if (!mask)
|
||||
continue;
|
||||
|
||||
if (priv->stbyctrl)
|
||||
oldval = readb(priv->base + STBCR(reg));
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
|
||||
oldval = readb(priv->base + priv->control_regs[reg]);
|
||||
else
|
||||
oldval = readl(priv->base + SMSTPCR(reg));
|
||||
oldval = readl(priv->base + priv->control_regs[reg]);
|
||||
newval = oldval & ~mask;
|
||||
newval |= priv->smstpcr_saved[reg].val & mask;
|
||||
if (newval == oldval)
|
||||
continue;
|
||||
|
||||
if (priv->stbyctrl) {
|
||||
writeb(newval, priv->base + STBCR(reg));
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
|
||||
writeb(newval, priv->base + priv->control_regs[reg]);
|
||||
/* dummy read to ensure write has completed */
|
||||
readb(priv->base + STBCR(reg));
|
||||
barrier_data(priv->base + STBCR(reg));
|
||||
readb(priv->base + priv->control_regs[reg]);
|
||||
barrier_data(priv->base + priv->control_regs[reg]);
|
||||
continue;
|
||||
} else
|
||||
writel(newval, priv->base + SMSTPCR(reg));
|
||||
writel(newval, priv->base + priv->control_regs[reg]);
|
||||
|
||||
/* Wait until enabled clocks are really enabled */
|
||||
mask &= ~priv->smstpcr_saved[reg].val;
|
||||
|
|
@ -879,7 +907,7 @@ static int cpg_mssr_resume_noirq(struct device *dev)
|
|||
continue;
|
||||
|
||||
for (i = 1000; i > 0; --i) {
|
||||
oldval = readl(priv->base + MSTPSR(reg));
|
||||
oldval = readl(priv->base + priv->status_regs[reg]);
|
||||
if (!(oldval & mask))
|
||||
break;
|
||||
cpu_relax();
|
||||
|
|
@ -887,8 +915,8 @@ static int cpg_mssr_resume_noirq(struct device *dev)
|
|||
|
||||
if (!i)
|
||||
dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
|
||||
priv->stbyctrl ? "STB" : "SMSTP", reg,
|
||||
oldval & mask);
|
||||
priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
|
||||
"STB" : "SMSTP", reg, oldval & mask);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -937,7 +965,23 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
|||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
|
||||
priv->stbyctrl = info->stbyctrl;
|
||||
priv->reg_layout = info->reg_layout;
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
|
||||
priv->status_regs = mstpsr;
|
||||
priv->control_regs = smstpcr;
|
||||
priv->reset_regs = srcr;
|
||||
priv->reset_clear_regs = srstclr;
|
||||
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
|
||||
priv->control_regs = stbcr;
|
||||
} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
|
||||
priv->status_regs = mstpsr_for_v3u;
|
||||
priv->control_regs = mstpcr_for_v3u;
|
||||
priv->reset_regs = srcr_for_v3u;
|
||||
priv->reset_clear_regs = srstclr_for_v3u;
|
||||
} else {
|
||||
error = -EINVAL;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
for (i = 0; i < nclks; i++)
|
||||
priv->clks[i] = ERR_PTR(-ENOENT);
|
||||
|
|
@ -1015,7 +1059,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
|
|||
return error;
|
||||
|
||||
/* Reset Controller not supported for Standby Control SoCs */
|
||||
if (info->stbyctrl)
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
|
||||
return 0;
|
||||
|
||||
error = cpg_mssr_reset_controller_register(priv);
|
||||
|
|
|
|||
|
|
@ -85,6 +85,12 @@ struct mssr_mod_clk {
|
|||
|
||||
struct device_node;
|
||||
|
||||
enum clk_reg_layout {
|
||||
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
|
||||
CLK_REG_LAYOUT_RZ_A,
|
||||
CLK_REG_LAYOUT_RCAR_V3U,
|
||||
};
|
||||
|
||||
/**
|
||||
* SoC-specific CPG/MSSR Description
|
||||
*
|
||||
|
|
@ -105,6 +111,7 @@ struct device_node;
|
|||
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
|
||||
* should not be disabled without a knowledgeable driver
|
||||
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
|
||||
* @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
|
||||
*
|
||||
* @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
|
||||
* Management, in addition to Module Clocks
|
||||
|
|
@ -112,10 +119,6 @@ struct device_node;
|
|||
*
|
||||
* @init: Optional callback to perform SoC-specific initialization
|
||||
* @cpg_clk_register: Optional callback to handle special Core Clock types
|
||||
*
|
||||
* @stbyctrl: This device has Standby Control Registers which are 8-bits
|
||||
* wide, no status registers (MSTPSR) and have different address
|
||||
* offsets.
|
||||
*/
|
||||
|
||||
struct cpg_mssr_info {
|
||||
|
|
@ -130,7 +133,7 @@ struct cpg_mssr_info {
|
|||
unsigned int num_core_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
unsigned int num_total_core_clks;
|
||||
bool stbyctrl;
|
||||
enum clk_reg_layout reg_layout;
|
||||
|
||||
/* Module Clocks */
|
||||
const struct mssr_mod_clk *mod_clks;
|
||||
|
|
@ -174,6 +177,7 @@ extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
|
|||
extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
|
||||
|
||||
void __init cpg_mssr_early_init(struct device_node *np,
|
||||
const struct cpg_mssr_info *info);
|
||||
|
|
|
|||
55
include/dt-bindings/clock/r8a779a0-cpg-mssr.h
Normal file
55
include/dt-bindings/clock/r8a779a0-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a779A0 CPG Core Clocks */
|
||||
#define R8A779A0_CLK_Z0 0
|
||||
#define R8A779A0_CLK_ZX 1
|
||||
#define R8A779A0_CLK_Z1 2
|
||||
#define R8A779A0_CLK_ZR 3
|
||||
#define R8A779A0_CLK_ZS 4
|
||||
#define R8A779A0_CLK_ZT 5
|
||||
#define R8A779A0_CLK_ZTR 6
|
||||
#define R8A779A0_CLK_S1D1 7
|
||||
#define R8A779A0_CLK_S1D2 8
|
||||
#define R8A779A0_CLK_S1D4 9
|
||||
#define R8A779A0_CLK_S1D8 10
|
||||
#define R8A779A0_CLK_S1D12 11
|
||||
#define R8A779A0_CLK_S3D1 12
|
||||
#define R8A779A0_CLK_S3D2 13
|
||||
#define R8A779A0_CLK_S3D4 14
|
||||
#define R8A779A0_CLK_LB 15
|
||||
#define R8A779A0_CLK_CP 16
|
||||
#define R8A779A0_CLK_CL 17
|
||||
#define R8A779A0_CLK_CL16MCK 18
|
||||
#define R8A779A0_CLK_ZB30 19
|
||||
#define R8A779A0_CLK_ZB30D2 20
|
||||
#define R8A779A0_CLK_ZB30D4 21
|
||||
#define R8A779A0_CLK_ZB31 22
|
||||
#define R8A779A0_CLK_ZB31D2 23
|
||||
#define R8A779A0_CLK_ZB31D4 24
|
||||
#define R8A779A0_CLK_SD0H 25
|
||||
#define R8A779A0_CLK_SD0 26
|
||||
#define R8A779A0_CLK_RPC 27
|
||||
#define R8A779A0_CLK_RPCD2 28
|
||||
#define R8A779A0_CLK_MSO 29
|
||||
#define R8A779A0_CLK_CANFD 30
|
||||
#define R8A779A0_CLK_CSI0 31
|
||||
#define R8A779A0_CLK_FRAY 32
|
||||
#define R8A779A0_CLK_DSI 33
|
||||
#define R8A779A0_CLK_VIP 34
|
||||
#define R8A779A0_CLK_ADGH 35
|
||||
#define R8A779A0_CLK_CNNDSP 36
|
||||
#define R8A779A0_CLK_ICU 37
|
||||
#define R8A779A0_CLK_ICUD2 38
|
||||
#define R8A779A0_CLK_VCBUS 39
|
||||
#define R8A779A0_CLK_CBFUSA 40
|
||||
#define R8A779A0_CLK_R 41
|
||||
#define R8A779A0_CLK_OSC 42
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
|
||||
59
include/dt-bindings/power/r8a779a0-sysc.h
Normal file
59
include/dt-bindings/power/r8a779a0-sysc.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the Power Domain Register Numbers (PDR)
|
||||
*/
|
||||
|
||||
#define R8A779A0_PD_A1E0D0C0 0
|
||||
#define R8A779A0_PD_A1E0D0C1 1
|
||||
#define R8A779A0_PD_A1E0D1C0 2
|
||||
#define R8A779A0_PD_A1E0D1C1 3
|
||||
#define R8A779A0_PD_A1E1D0C0 4
|
||||
#define R8A779A0_PD_A1E1D0C1 5
|
||||
#define R8A779A0_PD_A1E1D1C0 6
|
||||
#define R8A779A0_PD_A1E1D1C1 7
|
||||
#define R8A779A0_PD_A2E0D0 16
|
||||
#define R8A779A0_PD_A2E0D1 17
|
||||
#define R8A779A0_PD_A2E1D0 18
|
||||
#define R8A779A0_PD_A2E1D1 19
|
||||
#define R8A779A0_PD_A3E0 20
|
||||
#define R8A779A0_PD_A3E1 21
|
||||
#define R8A779A0_PD_3DG_A 24
|
||||
#define R8A779A0_PD_3DG_B 25
|
||||
#define R8A779A0_PD_A1CNN2 32
|
||||
#define R8A779A0_PD_A1DSP0 33
|
||||
#define R8A779A0_PD_A2IMP01 34
|
||||
#define R8A779A0_PD_A2DP0 35
|
||||
#define R8A779A0_PD_A2CV0 36
|
||||
#define R8A779A0_PD_A2CV1 37
|
||||
#define R8A779A0_PD_A2CV4 38
|
||||
#define R8A779A0_PD_A2CV6 39
|
||||
#define R8A779A0_PD_A2CN2 40
|
||||
#define R8A779A0_PD_A1CNN0 41
|
||||
#define R8A779A0_PD_A2CN0 42
|
||||
#define R8A779A0_PD_A3IR 43
|
||||
#define R8A779A0_PD_A1CNN1 44
|
||||
#define R8A779A0_PD_A1DSP1 45
|
||||
#define R8A779A0_PD_A2IMP23 46
|
||||
#define R8A779A0_PD_A2DP1 47
|
||||
#define R8A779A0_PD_A2CV2 48
|
||||
#define R8A779A0_PD_A2CV3 49
|
||||
#define R8A779A0_PD_A2CV5 50
|
||||
#define R8A779A0_PD_A2CV7 51
|
||||
#define R8A779A0_PD_A2CN1 52
|
||||
#define R8A779A0_PD_A3VIP0 56
|
||||
#define R8A779A0_PD_A3VIP1 57
|
||||
#define R8A779A0_PD_A3VIP2 58
|
||||
#define R8A779A0_PD_A3VIP3 59
|
||||
#define R8A779A0_PD_A3ISP01 60
|
||||
#define R8A779A0_PD_A3ISP23 61
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A779A0_PD_ALWAYS_ON 64
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
|
||||
Loading…
Reference in New Issue
Block a user