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clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()

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As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the Z clock on R-Car Gen2 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.

This includes implementing range checking.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190830134515.11925-7-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2019-08-30 15:45:13 +02:00
parent 56278c8fcb
commit 7aee839ed2
1 changed files with 13 additions and 10 deletions
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23
drivers/clk/renesas/rcar-gen2-cpg.c
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@ -63,19 +63,22 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
return div_u64((u64)parent_rate * mult, 32);
}
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int cpg_z_clk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned long prate = *parent_rate;
unsigned int mult;
unsigned long prate = req->best_parent_rate;
unsigned int min_mult, max_mult, mult;
if (!prate)
prate = 1;
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
if (max_mult < min_mult)
return -EINVAL;
mult = div64_ul(rate * 32ULL, prate);
mult = clamp(mult, 1U, 32U);
mult = div64_ul(req->rate * 32ULL, prate);
mult = clamp(mult, min_mult, max_mult);
return div_u64((u64)*parent_rate * mult, 32);
req->rate = div_u64((u64)prate * mult, 32);
return 0;
}
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@ -126,7 +129,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops cpg_z_clk_ops = {
.recalc_rate = cpg_z_clk_recalc_rate,
.round_rate = cpg_z_clk_round_rate,
.determine_rate = cpg_z_clk_determine_rate,
.set_rate = cpg_z_clk_set_rate,
};