AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

clk: qcom: Add WCSS gcc clock control for QCS404

Browse Source 
Add support for the WCSS QDSP gcc clock control used on qcs404
based devices. This would allow wcss remoteproc driver to control
the required gcc clocks to bring the subsystem out of reset.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Govind Singh 2019-07-26 14:53:26 +05:30 committed by Stephen Boyd
parent 56bf8740ff
commit 7d0c76bdf2
2 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/clk/qcom/gcc-qcs404.c
View File

@ -2604,6 +2604,32 @@ static struct clk_branch gcc_usb_hs_system_clk = {
}, },
}; };
static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wdsp_q6ss_ahbs_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wdsp_q6ss_axim_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_hw *gcc_qcs404_hws[] = { static struct clk_hw *gcc_qcs404_hws[] = {
&cxo.hw, &cxo.hw,
}; };
@ -2749,6 +2775,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr, [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
[GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
[GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
}; };
static const struct qcom_reset_map gcc_qcs404_resets[] = { static const struct qcom_reset_map gcc_qcs404_resets[] = {
@ -2774,6 +2803,7 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
[GCC_EMAC_BCR] = { 0x4e000 }, [GCC_EMAC_BCR] = { 0x4e000 },
[GCC_WDSP_RESTART] = {0x19000},
}; };
static const struct regmap_config gcc_qcs404_regmap_config = { static const struct regmap_config gcc_qcs404_regmap_config = {

3
include/dt-bindings/clock/qcom,gcc-qcs404.h
View File

@ -146,6 +146,8 @@
#define GCC_MDP_TBU_CLK 138 #define GCC_MDP_TBU_CLK 138
#define GCC_QDSS_DAP_CLK 139 #define GCC_QDSS_DAP_CLK 139
#define GCC_DCC_XO_CLK 140 #define GCC_DCC_XO_CLK 140
#define GCC_WCSS_Q6_AHB_CLK 141
#define GCC_WCSS_Q6_AXIM_CLK 142
#define GCC_CDSP_CFG_AHB_CLK 143 #define GCC_CDSP_CFG_AHB_CLK 143
#define GCC_BIMC_CDSP_CLK 144 #define GCC_BIMC_CDSP_CLK 144
#define GCC_CDSP_TBU_CLK 145 #define GCC_CDSP_TBU_CLK 145
@ -173,5 +175,6 @@
#define GCC_PCIE_0_CORE_STICKY_ARES 19 #define GCC_PCIE_0_CORE_STICKY_ARES 19
#define GCC_PCIE_0_SLEEP_ARES 20 #define GCC_PCIE_0_SLEEP_ARES 20
#define GCC_PCIE_0_PIPE_ARES 21 #define GCC_PCIE_0_PIPE_ARES 21
#define GCC_WDSP_RESTART 22
#endif #endif