forked from luck/tmp_suning_uos_patched
[ARM] 4601/1: KS8695: PCI support
This patch adds support for the PCI Host controller integrated in the Kendin/Micrel KS8695 processor. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
9b73e76f3c
commit
7d77ce8f67
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@ -9,7 +9,7 @@ obj-n :=
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obj- :=
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# PCI support is optional
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#obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_PCI) += pci.o
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# Board-specific support
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obj-$(CONFIG_MACH_KS8695) += board-micrel.o
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@ -40,7 +40,7 @@ static void __init micrel_init(void)
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printk(KERN_INFO "Micrel KS8695 Development Board initializing\n");
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#ifdef CONFIG_PCI
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// ks8695_init_pci(&micrel_pci);
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ks8695_init_pci(&micrel_pci);
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#endif
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/* Add devices */
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326
arch/arm/mach-ks8695/pci.c
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326
arch/arm/mach-ks8695/pci.c
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@ -0,0 +1,326 @@
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/*
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* arch/arm/mach-ks8695/pci.c
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*
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* Copyright (C) 2003, Micrel Semiconductors
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* Copyright (C) 2006, Greg Ungerer <gerg@snapgear.com>
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* Copyright (C) 2006, Ben Dooks
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* Copyright (C) 2007, Andrew Victor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/signal.h>
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#include <asm/mach/pci.h>
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#include <asm/hardware.h>
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#include <asm/arch/devices.h>
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#include <asm/arch/regs-pci.h>
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static int pci_dbg;
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static int pci_cfg_dbg;
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static void ks8695_pci_setupconfig(unsigned int bus_nr, unsigned int devfn, unsigned int where)
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{
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unsigned long pbca;
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pbca = PBCA_ENABLE | (where & ~3);
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pbca |= PCI_SLOT(devfn) << 11 ;
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pbca |= PCI_FUNC(devfn) << 8;
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pbca |= bus_nr << 16;
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if (bus_nr == 0) {
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/* use Type-0 transaction */
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__raw_writel(pbca, KS8695_PCI_VA + KS8695_PBCA);
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} else {
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/* use Type-1 transaction */
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__raw_writel(pbca | PBCA_TYPE1, KS8695_PCI_VA + KS8695_PBCA);
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}
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}
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/*
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* The KS8695 datasheet prohibits anything other than 32bit accesses
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* to the IO registers, so all our configuration must be done with
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* 32bit operations, and the correct bit masking and shifting.
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*/
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static int ks8695_pci_readconfig(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *value)
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{
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ks8695_pci_setupconfig(bus->number, devfn, where);
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*value = __raw_readl(KS8695_PCI_VA + KS8695_PBCD);
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switch (size) {
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case 4:
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break;
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case 2:
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*value = *value >> ((where & 2) * 8);
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*value &= 0xffff;
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break;
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case 1:
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*value = *value >> ((where & 3) * 8);
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*value &= 0xff;
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break;
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}
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if (pci_cfg_dbg) {
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printk("read: %d,%08x,%02x,%d: %08x (%08x)\n",
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bus->number, devfn, where, size, *value,
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__raw_readl(KS8695_PCI_VA + KS8695_PBCD));
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int ks8695_pci_writeconfig(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 value)
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{
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unsigned long tmp;
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if (pci_cfg_dbg) {
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printk("write: %d,%08x,%02x,%d: %08x\n",
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bus->number, devfn, where, size, value);
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}
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ks8695_pci_setupconfig(bus->number, devfn, where);
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switch (size) {
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case 4:
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__raw_writel(value, KS8695_PCI_VA + KS8695_PBCD);
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break;
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case 2:
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tmp = __raw_readl(KS8695_PCI_VA + KS8695_PBCD);
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tmp &= ~(0xffff << ((where & 2) * 8));
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tmp |= value << ((where & 2) * 8);
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__raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD);
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break;
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case 1:
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tmp = __raw_readl(KS8695_PCI_VA + KS8695_PBCD);
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tmp &= ~(0xff << ((where & 3) * 8));
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tmp |= value << ((where & 3) * 8);
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__raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static void ks8695_local_writeconfig(int where, u32 value)
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{
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ks8695_pci_setupconfig(0, 0, where);
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__raw_writel(value, KS8695_PCI_VA + KS8695_PBCD);
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}
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static struct pci_ops ks8695_pci_ops = {
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.read = ks8695_pci_readconfig,
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.write = ks8695_pci_writeconfig,
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};
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static struct pci_bus *ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys);
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}
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static struct resource pci_mem = {
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.name = "PCI Memory space",
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.start = KS8695_PCIMEM_PA,
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.end = KS8695_PCIMEM_PA + (KS8695_PCIMEM_SIZE - 1),
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.flags = IORESOURCE_MEM,
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};
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static struct resource pci_io = {
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.name = "PCI IO space",
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.start = KS8695_PCIIO_PA,
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.end = KS8695_PCIIO_PA + (KS8695_PCIIO_SIZE - 1),
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.flags = IORESOURCE_IO,
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};
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static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys)
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{
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if (nr > 0)
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return 0;
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request_resource(&iomem_resource, &pci_mem);
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request_resource(&ioport_resource, &pci_io);
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sys->resource[0] = &pci_io;
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sys->resource[1] = &pci_mem;
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sys->resource[2] = NULL;
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/* Assign and enable processor bridge */
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ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA);
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/* Enable bus-master & Memory Space access */
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ks8695_local_writeconfig(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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/* Set cache-line size & latency. */
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ks8695_local_writeconfig(PCI_CACHE_LINE_SIZE, (32 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
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/* Reserve PCI memory space for PCI-AHB resources */
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if (!request_mem_region(KS8695_PCIMEM_PA, SZ_64M, "PCI-AHB Bridge")) {
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printk(KERN_ERR "Cannot allocate PCI-AHB Bridge memory.\n");
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return -EBUSY;
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}
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return 1;
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}
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static inline unsigned int size_mask(unsigned long size)
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{
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return (~size) + 1;
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}
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static int ks8695_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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{
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unsigned long pc = instruction_pointer(regs);
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unsigned long instr = *(unsigned long *)pc;
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unsigned long cmdstat;
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cmdstat = __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS);
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printk(KERN_ERR "PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx [%s%s%s%s%s]\n",
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addr, fsr, regs->ARM_pc, regs->ARM_lr,
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cmdstat & (PCI_STATUS_SIG_TARGET_ABORT << 16) ? "GenTarget" : " ",
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cmdstat & (PCI_STATUS_REC_TARGET_ABORT << 16) ? "RecvTarget" : " ",
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cmdstat & (PCI_STATUS_REC_MASTER_ABORT << 16) ? "MasterAbort" : " ",
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cmdstat & (PCI_STATUS_SIG_SYSTEM_ERROR << 16) ? "SysError" : " ",
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cmdstat & (PCI_STATUS_DETECTED_PARITY << 16) ? "Parity" : " "
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);
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__raw_writel(cmdstat, KS8695_PCI_VA + KS8695_CRCFCS);
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/*
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* If the instruction being executed was a read,
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* make it look like it read all-ones.
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*/
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if ((instr & 0x0c100000) == 0x04100000) {
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int reg = (instr >> 12) & 15;
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unsigned long val;
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if (instr & 0x00400000)
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val = 255;
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else
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val = -1;
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regs->uregs[reg] = val;
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regs->ARM_pc += 4;
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return 0;
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}
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if ((instr & 0x0e100090) == 0x00100090) {
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int reg = (instr >> 12) & 15;
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regs->uregs[reg] = -1;
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regs->ARM_pc += 4;
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return 0;
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}
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return 1;
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}
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static void __init ks8695_pci_preinit(void)
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{
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/* stage 1 initialization, subid, subdevice = 0x0001 */
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__raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID);
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/* stage 2 initialization */
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/* prefetch limits with 16 words, retry enable */
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__raw_writel(0x40000000, KS8695_PCI_VA + KS8695_PBCS);
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/* configure memory mapping */
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__raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBA);
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__raw_writel(size_mask(KS8695_PCIMEM_SIZE), KS8695_PCI_VA + KS8695_PMBAM);
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__raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBAT);
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__raw_writel(0, KS8695_PCI_VA + KS8695_PMBAC);
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/* configure IO mapping */
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__raw_writel(KS8695_PCIIO_PA, KS8695_PCI_VA + KS8695_PIOBA);
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__raw_writel(size_mask(KS8695_PCIIO_SIZE), KS8695_PCI_VA + KS8695_PIOBAM);
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__raw_writel(KS8695_PCIIO_PA, KS8695_PCI_VA + KS8695_PIOBAT);
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__raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC);
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/* hook in fault handlers */
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hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch");
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hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch");
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}
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static void ks8695_show_pciregs(void)
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{
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if (!pci_dbg)
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return;
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printk(KERN_INFO "PCI: CRCFID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFID));
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printk(KERN_INFO "PCI: CRCFCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS));
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printk(KERN_INFO "PCI: CRCFRV = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFRV));
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printk(KERN_INFO "PCI: CRCFLT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFLT));
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printk(KERN_INFO "PCI: CRCBMA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCBMA));
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printk(KERN_INFO "PCI: CRCSID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCSID));
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printk(KERN_INFO "PCI: CRCFIT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFIT));
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printk(KERN_INFO "PCI: PBM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBM));
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printk(KERN_INFO "PCI: PBCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBCS));
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printk(KERN_INFO "PCI: PMBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBA));
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printk(KERN_INFO "PCI: PMBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAC));
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printk(KERN_INFO "PCI: PMBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAM));
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printk(KERN_INFO "PCI: PMBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAT));
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printk(KERN_INFO "PCI: PIOBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBA));
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printk(KERN_INFO "PCI: PIOBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAC));
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printk(KERN_INFO "PCI: PIOBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAM));
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printk(KERN_INFO "PCI: PIOBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAT));
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}
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static struct hw_pci ks8695_pci __initdata = {
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.nr_controllers = 1,
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.preinit = ks8695_pci_preinit,
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.setup = ks8695_pci_setup,
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.scan = ks8695_pci_scan_bus,
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.postinit = NULL,
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.swizzle = pci_std_swizzle,
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.map_irq = NULL,
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};
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void __init ks8695_init_pci(struct ks8695_pci_cfg *cfg)
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{
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if (__raw_readl(KS8695_PCI_VA + KS8695_CRCFRV) & CFRV_GUEST) {
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printk("PCI: KS8695 in guest mode, not initialising\n");
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return;
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}
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printk(KERN_INFO "PCI: Initialising\n");
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ks8695_show_pciregs();
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/* set Mode */
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__raw_writel(cfg->mode << 29, KS8695_PCI_VA + KS8695_PBM);
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ks8695_pci.map_irq = cfg->map_irq; /* board-specific map_irq method */
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pci_common_init(&ks8695_pci);
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}
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