forked from luck/tmp_suning_uos_patched
drm/i915: Mark untiled BLT commands as fenced on gen2/3
The BLT commands on gen2/3 utilize the fence registers and so we cannot modify any fences for the object whilst those commands are in flight. Currently we marked tiled commands as occupying a fence, but forgot to restrict the untiled commands from preventing a fence being assigned before they were completed. One side-effect is that we ten have to double check that a fence was allocated for a fenced buffer during move-to-active. Reported-by: Jiri Slaby <jirislaby@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43427 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47990 Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Testcase: i-g-t/tests/gem_tiled_after_untiled_blt Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1472,16 +1472,19 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
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list_move_tail(&obj->ring_list, &ring->active_list);
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obj->last_rendering_seqno = seqno;
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if (obj->fenced_gpu_access) {
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struct drm_i915_fence_reg *reg;
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BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
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obj->last_fenced_seqno = seqno;
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obj->last_fenced_ring = ring;
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reg = &dev_priv->fence_regs[obj->fence_reg];
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list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
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/* Bump MRU to take account of the delayed flush */
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if (obj->fence_reg != I915_FENCE_REG_NONE) {
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struct drm_i915_fence_reg *reg;
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reg = &dev_priv->fence_regs[obj->fence_reg];
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list_move_tail(®->lru_list,
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&dev_priv->mm.fence_list);
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}
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}
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}
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@ -498,8 +498,8 @@ pin_and_fence_object(struct drm_i915_gem_object *obj,
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if (ret)
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goto err_unpin;
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}
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obj->pending_fenced_gpu_access = true;
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}
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obj->pending_fenced_gpu_access = need_fence;
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}
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entry->offset = obj->gtt_offset;
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