forked from luck/tmp_suning_uos_patched
sh: delay slot future proofing via EXPMASK on SH-4A parts.
This implements EXPMASK initialization code for SH-4A parts, where it is possible to disable compat features that will go away in newer cores. Presently this includes disabling support for non-nop instructions in the rte delay slot, as well as a sleep instruction being placed in a delay slot (neither of which the kernel does any longer). As a result of this, any future offenders will have illegal slot exceptions generated for them. Associative writes for the memory-mapped cache array are still left enabled, until such a point that special cache operations for SH-4A are provided to move off of the current (and rather dated) SH-4 versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -3,7 +3,7 @@
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*
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* CPU init code
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*
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* Copyright (C) 2002 - 2007 Paul Mundt
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* Copyright (C) 2002 - 2009 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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@ -62,6 +62,37 @@ static void __init speculative_execution_init(void)
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#define speculative_execution_init() do { } while (0)
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#endif
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#ifdef CONFIG_CPU_SH4A
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#define EXPMASK 0xff2f0004
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#define EXPMASK_RTEDS (1 << 0)
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#define EXPMASK_BRDSSLP (1 << 1)
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#define EXPMASK_MMCAW (1 << 4)
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static void __init expmask_init(void)
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{
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unsigned long expmask = __raw_readl(EXPMASK);
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/*
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* Future proofing.
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*
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* Disable support for slottable sleep instruction
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* and non-nop instructions in the rte delay slot.
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*/
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expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP);
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/*
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* Enable associative writes to the memory-mapped cache array
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* until the cache flush ops have been rewritten.
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*/
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expmask |= EXPMASK_MMCAW;
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__raw_writel(expmask, EXPMASK);
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ctrl_barrier();
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}
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#else
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#define expmask_init() do { } while (0)
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#endif
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/* 2nd-level cache init */
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void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
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{
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@ -321,4 +352,5 @@ asmlinkage void __init sh_cpu_init(void)
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#endif
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speculative_execution_init();
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expmask_init();
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}
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