forked from luck/tmp_suning_uos_patched
net: nixge: Add support for 64-bit platforms
Add support for 64-bit platforms to driver. The hardware only supports 32-bit register accesses so the accesses need to be split up into two writes when setting the current and tail descriptor values. Signed-off-by: Moritz Fischer <mdf@kernel.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Moritz Fischer
David S. Miller
parent
02c7f38b7a
commit
7e8d5755be
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@ -18,8 +18,9 @@ if NET_VENDOR_NI
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config NI_XGE_MANAGEMENT_ENET
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tristate "National Instruments XGE management enet support"
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depends on ARCH_ZYNQ
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depends on HAS_IOMEM && HAS_DMA
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select PHYLIB
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select OF_MDIO
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help
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Simple LAN device for debug or management purposes. Can
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support either 10G or 1G PHYs via SFP+ ports.
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@ -106,10 +106,10 @@
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(NIXGE_JUMBO_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
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struct nixge_hw_dma_bd {
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u32 next;
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u32 reserved1;
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u32 phys;
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u32 reserved2;
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u32 next_lo;
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u32 next_hi;
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u32 phys_lo;
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u32 phys_hi;
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u32 reserved3;
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u32 reserved4;
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u32 cntrl;
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@ -119,11 +119,39 @@ struct nixge_hw_dma_bd {
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u32 app2;
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u32 app3;
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u32 app4;
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u32 sw_id_offset;
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u32 reserved5;
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u32 sw_id_offset_lo;
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u32 sw_id_offset_hi;
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u32 reserved6;
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};
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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#define nixge_hw_dma_bd_set_addr(bd, field, addr) \
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do { \
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(bd)->field##_lo = lower_32_bits(((u64)addr)); \
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(bd)->field##_hi = upper_32_bits(((u64)addr)); \
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} while (0)
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#else
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#define nixge_hw_dma_bd_set_addr(bd, field, addr) \
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((bd)->field##_lo = lower_32_bits((addr)))
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#endif
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#define nixge_hw_dma_bd_set_phys(bd, addr) \
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nixge_hw_dma_bd_set_addr((bd), phys, (addr))
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#define nixge_hw_dma_bd_set_next(bd, addr) \
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nixge_hw_dma_bd_set_addr((bd), next, (addr))
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#define nixge_hw_dma_bd_set_offset(bd, addr) \
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nixge_hw_dma_bd_set_addr((bd), sw_id_offset, (addr))
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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#define nixge_hw_dma_bd_get_addr(bd, field) \
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(dma_addr_t)((((u64)(bd)->field##_hi) << 32) | ((bd)->field##_lo))
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#else
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#define nixge_hw_dma_bd_get_addr(bd, field) \
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(dma_addr_t)((bd)->field##_lo)
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#endif
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struct nixge_tx_skb {
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struct sk_buff *skb;
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dma_addr_t mapping;
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@ -176,6 +204,15 @@ static void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
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writel(val, priv->dma_regs + offset);
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}
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static void nixge_dma_write_desc_reg(struct nixge_priv *priv, off_t offset,
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dma_addr_t addr)
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{
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writel(lower_32_bits(addr), priv->dma_regs + offset);
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
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#endif
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}
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static u32 nixge_dma_read_reg(const struct nixge_priv *priv, off_t offset)
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{
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return readl(priv->dma_regs + offset);
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@ -202,13 +239,22 @@ static u32 nixge_ctrl_read_reg(struct nixge_priv *priv, off_t offset)
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static void nixge_hw_dma_bd_release(struct net_device *ndev)
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{
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struct nixge_priv *priv = netdev_priv(ndev);
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dma_addr_t phys_addr;
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struct sk_buff *skb;
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int i;
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for (i = 0; i < RX_BD_NUM; i++) {
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dma_unmap_single(ndev->dev.parent, priv->rx_bd_v[i].phys,
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NIXGE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
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dev_kfree_skb((struct sk_buff *)
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(priv->rx_bd_v[i].sw_id_offset));
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phys_addr = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
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phys);
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dma_unmap_single(ndev->dev.parent, phys_addr,
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NIXGE_MAX_JUMBO_FRAME_SIZE,
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DMA_FROM_DEVICE);
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skb = (struct sk_buff *)
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nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
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sw_id_offset);
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dev_kfree_skb(skb);
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}
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if (priv->rx_bd_v)
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@ -231,6 +277,7 @@ static int nixge_hw_dma_bd_init(struct net_device *ndev)
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{
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struct nixge_priv *priv = netdev_priv(ndev);
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struct sk_buff *skb;
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dma_addr_t phys;
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u32 cr;
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int i;
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@ -259,27 +306,30 @@ static int nixge_hw_dma_bd_init(struct net_device *ndev)
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goto out;
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for (i = 0; i < TX_BD_NUM; i++) {
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priv->tx_bd_v[i].next = priv->tx_bd_p +
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sizeof(*priv->tx_bd_v) *
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((i + 1) % TX_BD_NUM);
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nixge_hw_dma_bd_set_next(&priv->tx_bd_v[i],
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priv->tx_bd_p +
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sizeof(*priv->tx_bd_v) *
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((i + 1) % TX_BD_NUM));
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}
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for (i = 0; i < RX_BD_NUM; i++) {
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priv->rx_bd_v[i].next = priv->rx_bd_p +
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sizeof(*priv->rx_bd_v) *
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((i + 1) % RX_BD_NUM);
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nixge_hw_dma_bd_set_next(&priv->rx_bd_v[i],
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priv->rx_bd_p
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+ sizeof(*priv->rx_bd_v) *
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((i + 1) % RX_BD_NUM));
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skb = netdev_alloc_skb_ip_align(ndev,
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NIXGE_MAX_JUMBO_FRAME_SIZE);
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if (!skb)
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goto out;
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priv->rx_bd_v[i].sw_id_offset = (u32)skb;
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priv->rx_bd_v[i].phys =
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dma_map_single(ndev->dev.parent,
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skb->data,
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NIXGE_MAX_JUMBO_FRAME_SIZE,
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DMA_FROM_DEVICE);
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nixge_hw_dma_bd_set_offset(&priv->rx_bd_v[i], skb);
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phys = dma_map_single(ndev->dev.parent, skb->data,
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NIXGE_MAX_JUMBO_FRAME_SIZE,
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DMA_FROM_DEVICE);
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nixge_hw_dma_bd_set_phys(&priv->rx_bd_v[i], phys);
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priv->rx_bd_v[i].cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
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}
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@ -312,18 +362,18 @@ static int nixge_hw_dma_bd_init(struct net_device *ndev)
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/* Populate the tail pointer and bring the Rx Axi DMA engine out of
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* halted state. This will make the Rx side ready for reception.
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*/
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nixge_dma_write_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
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nixge_dma_write_desc_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
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cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
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nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
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cr | XAXIDMA_CR_RUNSTOP_MASK);
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nixge_dma_write_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
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nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
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(sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1)));
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/* Write to the RS (Run-stop) bit in the Tx channel control register.
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* Tx channel is now ready to run. But only after we write to the
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* tail pointer register that the Tx channel will start transmitting.
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*/
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nixge_dma_write_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
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nixge_dma_write_desc_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
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cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
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nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
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cr | XAXIDMA_CR_RUNSTOP_MASK);
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@ -451,7 +501,7 @@ static int nixge_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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struct nixge_priv *priv = netdev_priv(ndev);
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struct nixge_hw_dma_bd *cur_p;
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struct nixge_tx_skb *tx_skb;
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dma_addr_t tail_p;
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dma_addr_t tail_p, cur_phys;
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skb_frag_t *frag;
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u32 num_frag;
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u32 ii;
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@ -466,15 +516,16 @@ static int nixge_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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return NETDEV_TX_OK;
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}
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cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
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skb_headlen(skb), DMA_TO_DEVICE);
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if (dma_mapping_error(ndev->dev.parent, cur_p->phys))
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cur_phys = dma_map_single(ndev->dev.parent, skb->data,
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skb_headlen(skb), DMA_TO_DEVICE);
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if (dma_mapping_error(ndev->dev.parent, cur_phys))
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goto drop;
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nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
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cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
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tx_skb->skb = NULL;
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tx_skb->mapping = cur_p->phys;
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tx_skb->mapping = cur_phys;
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tx_skb->size = skb_headlen(skb);
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tx_skb->mapped_as_page = false;
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@ -485,16 +536,17 @@ static int nixge_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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tx_skb = &priv->tx_skb[priv->tx_bd_tail];
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frag = &skb_shinfo(skb)->frags[ii];
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cur_p->phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
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skb_frag_size(frag),
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DMA_TO_DEVICE);
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if (dma_mapping_error(ndev->dev.parent, cur_p->phys))
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cur_phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
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skb_frag_size(frag),
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DMA_TO_DEVICE);
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if (dma_mapping_error(ndev->dev.parent, cur_phys))
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goto frag_err;
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nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
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cur_p->cntrl = skb_frag_size(frag);
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tx_skb->skb = NULL;
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tx_skb->mapping = cur_p->phys;
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tx_skb->mapping = cur_phys;
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tx_skb->size = skb_frag_size(frag);
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tx_skb->mapped_as_page = true;
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}
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@ -506,7 +558,7 @@ static int nixge_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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tail_p = priv->tx_bd_p + sizeof(*priv->tx_bd_v) * priv->tx_bd_tail;
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/* Start the transfer */
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nixge_dma_write_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
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nixge_dma_write_desc_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
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++priv->tx_bd_tail;
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priv->tx_bd_tail %= TX_BD_NUM;
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@ -537,7 +589,7 @@ static int nixge_recv(struct net_device *ndev, int budget)
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struct nixge_priv *priv = netdev_priv(ndev);
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struct sk_buff *skb, *new_skb;
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struct nixge_hw_dma_bd *cur_p;
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dma_addr_t tail_p = 0;
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dma_addr_t tail_p = 0, cur_phys = 0;
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u32 packets = 0;
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u32 length = 0;
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u32 size = 0;
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@ -549,13 +601,15 @@ static int nixge_recv(struct net_device *ndev, int budget)
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tail_p = priv->rx_bd_p + sizeof(*priv->rx_bd_v) *
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priv->rx_bd_ci;
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skb = (struct sk_buff *)(cur_p->sw_id_offset);
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skb = (struct sk_buff *)nixge_hw_dma_bd_get_addr(cur_p,
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sw_id_offset);
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length = cur_p->status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
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if (length > NIXGE_MAX_JUMBO_FRAME_SIZE)
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length = NIXGE_MAX_JUMBO_FRAME_SIZE;
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dma_unmap_single(ndev->dev.parent, cur_p->phys,
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dma_unmap_single(ndev->dev.parent,
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nixge_hw_dma_bd_get_addr(cur_p, phys),
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NIXGE_MAX_JUMBO_FRAME_SIZE,
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DMA_FROM_DEVICE);
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@ -579,16 +633,17 @@ static int nixge_recv(struct net_device *ndev, int budget)
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if (!new_skb)
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return packets;
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cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
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NIXGE_MAX_JUMBO_FRAME_SIZE,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(ndev->dev.parent, cur_p->phys)) {
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cur_phys = dma_map_single(ndev->dev.parent, new_skb->data,
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NIXGE_MAX_JUMBO_FRAME_SIZE,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(ndev->dev.parent, cur_phys)) {
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/* FIXME: bail out and clean up */
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netdev_err(ndev, "Failed to map ...\n");
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}
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nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
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cur_p->cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
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cur_p->status = 0;
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cur_p->sw_id_offset = (u32)new_skb;
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nixge_hw_dma_bd_set_offset(cur_p, new_skb);
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++priv->rx_bd_ci;
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priv->rx_bd_ci %= RX_BD_NUM;
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@ -599,7 +654,7 @@ static int nixge_recv(struct net_device *ndev, int budget)
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ndev->stats.rx_bytes += size;
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if (tail_p)
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nixge_dma_write_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
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nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
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return packets;
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}
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@ -637,6 +692,7 @@ static irqreturn_t nixge_tx_irq(int irq, void *_ndev)
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struct nixge_priv *priv = netdev_priv(_ndev);
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struct net_device *ndev = _ndev;
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unsigned int status;
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dma_addr_t phys;
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u32 cr;
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status = nixge_dma_read_reg(priv, XAXIDMA_TX_SR_OFFSET);
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@ -650,9 +706,11 @@ static irqreturn_t nixge_tx_irq(int irq, void *_ndev)
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return IRQ_NONE;
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}
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if (status & XAXIDMA_IRQ_ERROR_MASK) {
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phys = nixge_hw_dma_bd_get_addr(&priv->tx_bd_v[priv->tx_bd_ci],
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phys);
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netdev_err(ndev, "DMA Tx error 0x%x\n", status);
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netdev_err(ndev, "Current BD is at: 0x%x\n",
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(priv->tx_bd_v[priv->tx_bd_ci]).phys);
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netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
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cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
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/* Disable coalesce, delay timer and error interrupts */
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@ -678,6 +736,7 @@ static irqreturn_t nixge_rx_irq(int irq, void *_ndev)
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struct nixge_priv *priv = netdev_priv(_ndev);
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struct net_device *ndev = _ndev;
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unsigned int status;
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dma_addr_t phys;
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u32 cr;
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status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
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@ -697,9 +756,10 @@ static irqreturn_t nixge_rx_irq(int irq, void *_ndev)
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return IRQ_NONE;
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}
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if (status & XAXIDMA_IRQ_ERROR_MASK) {
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phys = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[priv->rx_bd_ci],
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phys);
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netdev_err(ndev, "DMA Rx error 0x%x\n", status);
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netdev_err(ndev, "Current BD is at: 0x%x\n",
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(priv->rx_bd_v[priv->rx_bd_ci]).phys);
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netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
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cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
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/* Disable coalesce, delay timer and error interrupts */
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@ -735,10 +795,10 @@ static void nixge_dma_err_handler(unsigned long data)
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tx_skb = &lp->tx_skb[i];
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nixge_tx_skb_unmap(lp, tx_skb);
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cur_p->phys = 0;
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nixge_hw_dma_bd_set_phys(cur_p, 0);
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cur_p->cntrl = 0;
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cur_p->status = 0;
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cur_p->sw_id_offset = 0;
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nixge_hw_dma_bd_set_offset(cur_p, 0);
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}
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for (i = 0; i < RX_BD_NUM; i++) {
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@ -779,18 +839,18 @@ static void nixge_dma_err_handler(unsigned long data)
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/* Populate the tail pointer and bring the Rx Axi DMA engine out of
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* halted state. This will make the Rx side ready for reception.
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*/
|
||||
nixge_dma_write_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
|
||||
nixge_dma_write_desc_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
|
||||
cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
|
||||
nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,
|
||||
cr | XAXIDMA_CR_RUNSTOP_MASK);
|
||||
nixge_dma_write_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
|
||||
nixge_dma_write_desc_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
|
||||
(sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
|
||||
|
||||
/* Write to the RS (Run-stop) bit in the Tx channel control register.
|
||||
* Tx channel is now ready to run. But only after we write to the
|
||||
* tail pointer register that the Tx channel will start transmitting
|
||||
*/
|
||||
nixge_dma_write_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
|
||||
nixge_dma_write_desc_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
|
||||
cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
|
||||
nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,
|
||||
cr | XAXIDMA_CR_RUNSTOP_MASK);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user